System and method for referencing interrupt request information in a programmable interrupt controller

An interrupt controller, comprising:

• interrupt request interface circuitry configured to receive and process a plurality of interrupt requests, wherein said interrupt request interface circuitry assigns an unique interrupt identification code to each one of said plurality of interrupt requests;
• storage circuitry coupled to said interrupt request interface circuitry, wherein said interrupt request interface circuitry stores a priority level, an interrupt vector, and an interrupt status for each one of said plurality of interrupt requests in said storage circuitry, wherein said unique interrupt identification code is used to reference said information stored in said storage circuit corresponding to said one of said plurality of interrupt requests assigned said unique interrupt identification code;
• a first processor interface circuitry coupled to said interrupt request interface circuitry and coupled to said storage circuitry, wherein said first processor interface circuitry interfaces to a first CPU;
• a second processor interface circuitry coupled to said interrupt request interface circuitry and coupled to said storage circuitry, wherein said second processor interface circuitry interfaces to a second CPU;
• wherein said interrupt request interface circuitry determines which ones of said plurality of interrupt requests are destined for said first CPU and which ones of said plurality of interrupt requests are destined for said second CPU, wherein said interrupt request circuitry provides said unique interrupt identification code for each one of said plurality of interrupt requests destined for said first CPU to said first processor interface circuitry, and wherein said interrupt request circuitry provides said unique interrupt identification code for each one of said plurality of interrupt requests destined for said second CPU to said second processor interface circuitry;
• wherein said first processor interface circuitry stores said unique interrupt identification code for each one of said plurality of interrupt requests destined for said first CPU, and wherein said first processor interface circuitry uses each said stored unique interrupt identification code for each one of said plurality of interrupt requests destined for said first CPU to access said information in said storage circuitry;
• and
• wherein said second processor interface circuitry stores said unique interrupt identification code for each one of said plurality of interrupt requests destined for said second CPU, and wherein said second processor interface circuitry uses each said stored unique interrupt identification code for each one of said plurality of interrupt requests destined for said second CPU to access said information in said storage circuitry.

A computer system, comprising:

• an interrupt controller configured to receive a plurality of interrupt requests and configured to provide a first processor interrupt signal and a second processor interrupt signal;
• a first CPU coupled to said interrupt controller and configured to receive said first processor interrupt signal;
• a second CPU coupled to said interrupt controller and configured to receive said second processor interrupt signal;
• a memory coupled to the first and second CPU to provide interrupt service routines for execution, wherein each CPU is configured to retrieve one of the interrupt service routines when provided with a corresponding interrupt vector;
• and
• a plurality of devices coupled to said interrupt controller, wherein each one of said plurality of devices is configured to generate one of said plurality of interrupt request signals;
• wherein said interrupt controller comprises:
• interrupt request interface circuitry configured to receive and process said plurality of interrupt requests, wherein said interrupt request interface circuitry assigns a unique interrupt identification code to each one of said plurality of interrupt requests;
• storage circuitry coupled to said interrupt request interface circuitry, wherein said interrupt request interface circuitry stores information for each one of said plurality of interrupt requests in said storage circuitry, wherein the information for each one of said plurality of interrupt requests includes an interrupt priority, an interrupt status, and an interrupt vector, and wherein said unique interrupt identification code is used to reference said information stored in said storage circuit corresponding to said one of said plurality of interrupt requests assigned said unique interrupt identification code;
• a first processor interface circuit coupled to said interrupt request interface circuitry and coupled to said storage circuitry, wherein said first processor interface circuit interfaces to said first CPU;
• a second processor interface circuit coupled to said interrupt request interface circuitry and coupled to said storage circuitry, wherein said second processor interface circuit interfaces to said second CPU;
• wherein said interrupt request interface circuitry determines which ones of said plurality of interrupt requests are destined for said first CPU and which ones of said plurality of interrupt requests are destined for said second CPU, wherein said interrupt request circuitry provides said unique interrupt identification code for each one of said plurality of interrupt requests destined for said first CPU to said first processor interface circuit, and wherein said interrupt request circuitry provides said unique interrupt identification code for each one of said plurality of interrupt requests destined for said second CPU to said second processor interface circuit;
• wherein said first processor interface circuit stores said unique interrupt identification code for each one of said plurality of interrupt requests destined for said first CPU, and wherein said first processor interface circuit uses each said stored unique interrupt identification code for each one of said plurality of interrupt requests destined for said first CPU to access said information in said storage circuitry;
• and
• wherein said second processor interface circuit stores said unique interrupt identification code for each one of said plurality of interrupt requests destined for said second CPU, and wherein said second processor interface circuit uses each said stored unique interrupt identification code for each one of said plurality of interrupt requests destined for said second CPU to access said information in said storage circuitry.

A method for handling interrupt requests within an interrupt controller, comprising:

• receiving a plurality of interrupt requests;
• assigning an unique interrupt identification code to each one of said interrupt requests;
• storing information for each one of said plurality of interrupt requests, wherein said information includes a status, an interrupt vector, and a priority level, wherein said information is referenced by said unique interrupt identification code, and wherein said priority level is determined from a number of different priority levels;
• storing said unique interrupt identification code for each one of said interrupt requests in one of a number of entries in a interrupt nesting buffer, wherein said number of entries corresponds to said number of priority levels;
• determining which one of said number of entries containing said unique identification code for one of said interrupt requests corresponds to a highest priority level;
• after said determining, using said interrupt identification code from said highest priority one of said number of entries to access said information for said one of said plurality of interrupt requests corresponding to said highest priority entry;
• issuing a processor interrupt to one of a plurality of CPUs according to said accessed information.