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US 5,850,556 AGranted
Interruptible state machine
AssigneeCypress Semiconductor Corporation
InventorEdward L. Grivna
Life of this patent
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Abstract
An interruptible state machine includes a state machine and an interrupt processor. The interrupt processor minimizes the required total number of states for the state machine when it must return to its next "normal" state after an input or interrupt that may occur at any of its normal states. In response to the interrupt, the interrupt processor stores the next state, processes the interrupt, and restores the next state after processing the interrupt.
Claims11
An interruptible state machine comprising:
- a next state decoder having a next state;
- an interrupt processor including a multiplexor, interrupt vectors, and a storage register for storing said next state;
- and
- a state register in communication with said next state decoder and said interrupt processor for receiving said next state from said next state decoder in absence of an interrupt or for receiving an interrupt vector from said interrupt processor in the presence of said interrupt;
- wherein said multiplexor is configured for holding up said next state from loading into said state register and allowing one of said interrupt vectors to load into said state register.
2 more elements
Dependencies are inferred from the claim text.