Compiler and processor for processing loops at high speed

A processor for executing a program containing a machine-language instruction sequence which includes certain instructions, namely a first loop exclusive instruction and a second loop exclusive instruction, comprising:

• a pipeline, comprising:
• a fetching unit for fetching instructions one by one from the machine-language instruction sequence;
• a decoding unit for decoding the instructions fetched by the fetching unit;
• and
• an executing unit for executing the instructions decoded by the decoding unit;
• a branch target storage means;
• a registering means for, after the decoding unit has decoded a first loop exclusive instruction, registering branch target information in the branch target storage means, wherein the first loop exclusive instruction includes a first code which explicitly instructs the processor to register the branch target information in the branch target storage means prior to execution of the program;
• and
• a branch executing means for, after the decoding unit has decoded a second loop exclusive instruction, judging whether to execute a loop, if judges to execute, reading the branch target information registered in the branch target storage means, and controlling the pipeline so that the program executes the loop using the read branch target information, wherein each of the second loop exclusive instructions includes a second code which explicitly instructs the processor to judge whether to execute a loop without first determining whether a branch target address is registered in the dedicated branch target storage means, instructs the processor to read the branch target information registered in the branch target storage means when the processor judges to execute, and instructs the processor to control the pipeline so that the program executes the loop using the branch target information.

A processor for executing a program containing a machine-language instruction sequence which includes certain instructions, namely a first loop exclusive instruction and a second loop exclusive instruction, comprising:

• a pipeline, comprising:
• a fetching unit for fetching instructions one by one from the machine-language instruction sequence;
• a decoding unit for decoding the instructions fetched by the fetching unit;
• and
• an executing unit for executing the instructions decoded by the decoding unit;
• a branch target storage means;
• a registering means for, after the decoding unit has decoded a first loop exclusive instruction, registering branch target information in the branch target storage means, wherein the first loop exclusive instruction includes a first code which explicitly instructs the processor to register the branch target information in the branch target storage means prior to execution of the program;
• a branch executing means for, after the decoding unit has decoded a second loop exclusive instruction, judging whether to execute a loop, if judges to execute, reading the branch target information registered in the branch target storage means, and controlling the pipeline so that the program executes the loop using the read branch target information, wherein each of the second loop exclusive instructions includes a second code which explicitly instructs the processor to judge whether to execute a loop without first determining whether a branch target address is registered in the dedicated branch target storage means, instructs the processor to read the branch target information registered in the branch target storage means when the processor judges to execute, and instructs the processor to control the pipeline so that the program executes the loop using the branch target information;
• and
• a clearing means for, after the decoding unit has decoded a third loop exclusive instruction, clearing the branch target information registered in the branch target storage means, wherein the third loop exclusive instruction includes a third code which explicitly instructs the processor to clear the branch target information registered in the branch target storage means.

A compiler for compiling a source program and generating a program containing a machine-language instruction sequence for a processor, comprising:

• a loop detecting means for detecting certain loops from the source program and extracting information of the detected loops from the source program, the extracted information being used to specify the certain loops;
• and
• a high-speed loop applying means, comprising;
• a first loop exclusive instruction generating unit for generating a first loop exclusive instruction which indicates a succeeding instruction is an entry of a loop and placing the first loop exclusive instruction immediately before the entry of the loop in the machine-language instruction sequence;
• wherein the first loop exclusive instruction includes a first code which explicitly instructs the processor to register branch target information in a dedicated branch target storage means of the processor prior to execution of the program and independent from the contents of the certain loops;
• and
• a second loop exclusive instruction generating unit for generating second loop exclusive instructions which direct the program to branch to the entry of the loop and placing the second loop exclusive instructions at places from where the program branches to the entry of the loop, the first loop exclusive instruction generating unit and the second loop exclusive instruction generating unit operating based on the information extracted by the loop detecting means, wherein each of the second loop exclusive instructions includes a second code which explicitly instructs the processor to determine whether to execute a loop without first determining whether a branch target address is registered in the dedicated branch target storage means and only reads the branch target information registered in the dedicated branch storage means when the processor determines to execute a loop;
• the second code further instructing the processor to execute the loop using the branch target information.