Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return

A method of operating a pipelined microprocessor to speculatively execute instructions, comprising the steps of:

• fetching a first instruction from an instruction memory, responsive to an instruction address;
• decoding the first instruction fetched from the instruction memory;
• executing the decoded first instruction in one of a plurality of execution units, which stores a speculative target instruction address and speculative register value in a branch prediction function;
• fetching a second instruction which according to said branch prediction function's prediction, corresponds to said speculative target instruction address and speculative register value;
• fetching and decoding a third and subsequent instructions using the speculative target instruction address;
• and
• executing said third and subsequent instructions and thereby supplying said speculative register value for use by the third and subsequent instructions until said second instruction executes and provides an actual target instruction address and an actual register value.

A microprocessor-based computer system, comprising:

• an input device;
• a display system;
• a main memory;
• and
• a microprocessor, coupled to the input device, display system and main memory, and comprising:
• a plurality of execution units for executing a plurality of instructions simultaneously;
• an instruction decode unit, for decoding instructions;
• an instruction memory for storing instructions according to instruction addresses;
• a fetch unit, for retrieving instructions from the instruction memory for a series of instructions, said fetch unit operating to retrieve a second instruction simultaneously with the execution of a first instruction by one of the plurality of execution units, said fetch unit comprising:
• a branch prediction function for storing a speculative target instruction address upon execution of said first instruction corresponding to the address from which to continue execution subsequent to execution of a return-type instruction, and for storing, in association with the speculative target instruction address, a speculative register value for use in speculatively executing instruction following said return-type instruction.