Microprocessor instruction hedge-fetching in a multiprediction branch environment

Abstract

An apparatus for fetching instructions in a computer system is disclosed. The apparatus includes a cache circuit for holding a sub-set of main store, a buffer circuit for holding instructions fetched from the cache for dispatch to a plurality of execution units, and a branch resolution unit. A first tag associated with each instruction to be dispatched is generated that identifies the instruction while it is in process. The execution units execute dispatched instructions and provide resulting condition codes and first tag for each instruction that is completed. The branch resolution unit, fetches a not guessed instruction stream from the cache such that the not guessed instruction stream is available to the instruction buffer during the same cycle that the guess is resolved. The branch resolution unit also includes means for guessing the result of a branch instruction and means for fetching a guessed instruction stream to be fetched.

Dependencies are inferred from the claim text.