Data processing apparatus having a clock control unit for decreasing power consumption of a central processing unit

A data processing apparatus comprising:

• a CPU coupled to a clock line for receiving a clock signal therethrough, said CPU for issuing a data read request;
• a device subjected to a data read operation;
• and
• a BCU coupled between said CPU and said device for performing a data read bus cycle on said device in response to said data read request,
• said device responding to said data read bus cycle by performing a data read operation and returning read data to said BCU,
• said BCU including a clock control circuit which is inserted in series in said clock line and responds to said data read request to prevent said clock signal from being supplied to said CPU for a predetermined period of time, and said BCU further including a register storing control data, said control data being read out of said register in response to said data read request and transferred to said clock control circuit to define at least one part of said predetermined period of time,
• whereby at least one clock of said clock signal is not supplied to said CPU during said predetermined period of time.