Method for enforcing true dependencies in an out-of-order processor

A method for detecting dependencies between a first instruction and a second instruction operating in a processor, said first instruction specifying at least a destination register, said second instruction specifying a first source register, a second source register, and a destination register, the method comprising the steps of:

• providing a table for storing dependency information regarding live instructions in a processor, said dependency information comprising an instruction identifier identifying said first instruction, and a destination register identifier identifying said destination register of said first instruction;
• associating a process identifier with said first instruction indicating which of a number of independent processes generated said first instruction;
• storing dependency information regarding said first instruction in said table;
• comparing said destination register identifier of said first instruction to said first and second source registers of said second instruction;
• and
• in response to said comparing step, indicating a dependency of said second instruction upon said first instruction if said destination register identifier corresponds to said first or second source registers of said second instruction.