Bus timing protocol for a data storage system
AssigneeEMC Corporation
InventorsJohn K. Walton, Eli Leshem
Life of this patent
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Abstract
In an data storage system having a bank of disk drives an addressable memory has a buffer memory coupled to a bus, a random access memory coupled to the buffer memory, an internal clock, and a logic network. The logic network is coupled to the bus and configured to transfer data among the buffer memory, the random access memory, and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. The addressable memory is included in an interface and further includes a master memory unit and a slave memory unit.
Claims10
A data storage system wherein a computer having processors for processing data is coupled to a bank of disk drives through an interface, such interface comprising:
- (A) a bus;
- (B) a plurality of controllers each one thereof being adapted to assert on the bus during a controller initiated bus assert interval:
- (a) a memory address;
- aid (b) a command, such command including:
- (i) either a write operation request or a read operation request;
- and, (ii) when a write operation is requested during a subsequent bus grant interval, data and bus write clock pulses;
- (C) at least one addressable memory adapted to produce on the bus a bus grant signal to initiate the bus grant interval in response to the controller bus assertion when such addressed memory is available to respond to the read or write operation request provided by the controller, and:
- (a) in response to a read operation request by the controller, provide, during the bus grant interval, data at the address provided by the controller during the bus assert interval along with bus read clock pulges;
- (b) in response to a write operation request by the controller, write, during the bus grant interval, the data on the bus at the address provided by the controller during the bus assert interval, such data being written into the addressable memory in response the bus write clock pulses produced by the controller on the bus during the bus grant interval;
- and,
- (c) upon completion of the read or write operation requested by the controller, remove the bus grant signal to terminate the bus grant interval;
- and
- (D) wherein each one of the controllers is adapted to provide on the bus another address and command after termnination of a previous bus assertion interval.
A data storage system wherein a computer having processors for processing data is coupled to a bank of disk drives through an interface, such interface comprising:
- (A) a bus having an bus-select/address/command portion and a bus-grant/data/clock-pulse portion;
- (B) at least one addressable memory;
- (C) a plurality of controllers each one thereof being adapted:
- (a) to assert on the bus-select/command/address portion of the bus during a controller initiated bus assert interval a command including:
- (i) either a write operation request or a read operation request;
- and (ii) an address to address one of the at least one addressable memory selected by the controller to respond to the write operation or read operation command;
- and
- (b) to produce data and bus write clock pulses on the bus-grant/data/clock-pulse portion of the bus when a write operation is requested during a subsequent bus grant interval produced by the addressed memory;
- (D) such addressed memory being adapted:
- (a) to produce on the bus-grant/data/clock-pulse portion of the bus a bus grant signal to initiate the bus grant interval when the addressed memory is available to respond to the read or write operation request;
- (b) to provide on the bus-grant/data/clock-pulse portion of the bus during the bus grant interval in response to the read operation request by the controller:
- (i) data at the address provided by the controller during the bus assert interval;
- and (ii) bus read clock pulses;
- (c) to write, in response to the write operation request by the controller during the bus grant interval, the data on the bus-grant/data/clock-pulse portion of the bus into the addressed memory in response the bus write clock pulses produced by the controller on the bus-grant/data/clock-pulse portion of the bus;
- and,
- (d) to remove the bus grant signal from the bus-grant/data/clock-pulse portion of the bus upon completion of the read or write operation requested by the controller terminating the bus grant interval;
- and
- (E) wherein each one of the controllers is adapted to provide on the bus-select/address/command portion of the bus another address and command after termination of a previous bus assertion interval.
Dependencies are inferred from the claim text.