Apparatus and method for interprocessor communication

A data processing system wherein a command instruction signal group generated in a first central processing unit is executed in a second central processing unit, said data processing system comprising:

• a system bus;
• and
• a plurality of central processing units coupled to said system bus, said plurality of central processing units including a source central processing unit and a target central processing unit, said central processing units receiving signal groups from and applying signal groups to said system bus, each of said central processing units including;
• execution apparatus for processing data signal groups in said each central processing unit in response to control signals resulting from decoding of instruction signal groups, wherein said source central processing unit includes condition apparatus for generating a command signal group in response to and determined by a preestablished condition in said source central processing unit, said command signal group being applied to said system bus along with a target central processing unit address signal group,
• said target central processing unit including an interface means for identifying said target processing unit address signal group and for storing said command signal group applied to said system bus having said target processing unit address signal group;
• said target central processing unit including decode logic coupled to at least one preselected component of said second central processing unit execution apparatus, said decode logic decoding said stored command signal group, said decode logic applying control signals resulting from said decoding to said preselected component of said target central processing unit thereby executing said command signal group without software intervention, wherein storing said command signal group in said target central processing unit suspends execution by said execution apparatus of said target central processing unit of a currently executing instruction signal group sequence upon completion of a currently executing instruction signal group, wherein said control signals are applied to said preselected component upon completion of execution of said currently executing instruction signal group.

In a multiprogrammed, multiprocessor data processing system, interprocessor command instruction apparatus in each processor whereby a source processor can apply control signals to preselected apparatus of an instruction execution unit of a target processor, each of said processors coupled to a system bus, said instruction execution unit of each of said processors processing data signal groups in response to instruction signal groups, said interprocessor command instruction apparatus comprising:

• means for generating a command signal group in response to a preestablished processor condition, wherein said command signal group is determined by said preestablished condition;
• transfer means for including an address signal group with said command signal group, said address signal group identifying a target processor, said transfer means applying said address signal group and said command signal group to said system bus;
• storage means coupled to said system bus and responsive to said address signal group for storing said command signal group in said target processor;
• signaling means responsive to said command signal group stored in said storage means for signaling to said target processor instruction execution unit a presence in said storage means of said command signal group, said signaling by said signaling means causing said target processor instruction execution apparatus to suspend instruction signal group execution upon completion of a currently executing instruction signal group;
• and
• decoding logic coupled between said storage means and said instruction execution unit apparatus, said decoding logic decoding said command signal group and applying control signals resulting from said decoding to said target processor instruction execution unit apparatus when said command signal group is stored in said storage means and target processor instruction execution is suspended, wherein said control signals cause an instruction identified by said command signal group to be executed by said target processor instruction execution unit apparatus without software intervention, wherein suspended execution of instruction signal groups is resumed in said target processor instruction execution unit upon completion of execution of said command signal group.

A data processing system having a plurality of processors and a main memory unit coupled by a system bus, said data processing system being capable of transferring signal groups from a first processor to an addressed processor of said plurality of processors, wherein each of said plurality of processors comprises:

• processing means including an execution unit and an instruction register for executing instruction signal groups entered in said instruction register of said processing means;
• identification means for identifying each of a plurality of preselected conditions in a processor, said identification means providing a command signal group in response to a preselected condition, said command signal group determined by said preselected condition;
• a storage apparatus;
• transfer means for transferring signal groups to and from said system bus, said transfer means of a first processor applying said command signal group and a related address signal group identifying an addressed processor to said system bus, said transfer means storing said command signal group from said system bus in said storage apparatus of said addressed processor when said related address signal group with said command signal group identifies an addressed processor which includes said transfer means;
• decoding logic responsive to said command signal group in said storage apparatus for decoding said command signal group and for applying control signals resulting from said decoding to a preselected component of said execution unit, said control signals resulting in execution of an instruction identified by said command signal group in said addressed processor;
• and
• signal means coupled to said transfer means for signaling to said processing means a storage of said command signal group in said processor storage apparatus, said signal means causing said processing means to suspend instruction execution until completion of application of said control signals to said preselected component.

A data processing system having a plurality of processors, each processor including apparatus for applying control signals to a preselected component of instruction execution apparatus in said each processor, said control signals and said preselected component identified by a one of a plurality of command signal groups generated in a different processor, each command signal group generated in response to and determined by a preestablished condition in said different processor, said one command signal group being transferred to said each processor from said different processor, said each processor exchanging signals with said different processor by a system bus, said one command signal group to be transferred to said each processor from said different processor being applied to said system bus along with an address signal group identifying said each processor receiving said command signal group from said system bus, wherein instructions entered in said processor are executed by an instruction execution unit, said apparatus comprising:

• interface means coupled to said system bus, said interface means for transferring said one command signal group from said system bus to a processor having said interface means when said address signal group with said one command signal group identifies said processor having the interface means;
• storage apparatus for storing said one command signal group transferred by said interface means from said system bus;
• decoder logic coupled to predetermined instruction execution unit apparatus and to said storage apparatus, said decoder logic decoding said one command signal group stored in said storage apparatus and applying control signals resulting from said decoding to said predetermined instruction execution unit apparatus, said control signals executing a command represented by said command signal group, said control signals and said predetermined instruction execution unit apparatus determined by said one command signal group;
• and
• apparatus responsive to a storing of said one command signal group in said storage apparatus for applying a first signal to said instruction execution unit, said first signal preventing further instruction execution following completion of a currently executing instruction by said instruction execution unit of instructions entered in said instruction execution unit until activity resulting from application of said control signals to said predetermined instruction execution unit apparatus is complete.