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AssigneeUnisys Corporation
InventorsBruce Ernest Whittaker, James Henry Jeppesen, III
Estimating the term…
A central processing module (CPM) uses a data path array interface connecting dual system busses to a main memory module and I/O module. A maintenance controller in the CPM manages a programmable array logic unit controller to read out microcode words in the main memory module to verify their accuracy by comparison with an original data base of microcode words in a flash memory which was earlier pre-loaded from a maintenance subsystem. A high speed auxiliary data bus controlled by the programmable array logic controller, provides a high speed transfer channel for moving the main memory words to the maintenance controller which can then institute a verification procedure for each memory word.
In a network wherein a maintenance subsystem preloads blocks of microcode data to a flash memory unit appended to a maintenance controller means in a central processing module (CPM) with a high speed processor data bus connecting a central processor, a microcode RAM and data path array, a system for the rapid readout and verification of blocks of microcode data residing in a main memory module during initialization, comprising:
A method, during system initialization, for the fast readout of blocks of microcode words from a main memory module and for integrity verification by a maintenance controller in a central processing module having a central processor utilizing a high speed processor bus which enables data transfers between an associated microcode RAM and a data path array means, said method comprising the steps of:
In a network initialization operation wherein a central processing module has a maintenance controller means with flash memory preloaded with original blocks of microcode data words from a maintenance subsystem, and wherein said central processing module includes a central processor having a high speed processor bus connected to a data path array means, an interface system for high speed data transfer, at speeds comparable to said processor bus, of blocks of microcode words from a main memory module through said data path array means to said maintenance controller means for verification against said original blocks of microcode data words, said interface system comprising:
A system for high speed delivery of channel microcode data during network initialization to a main memory module with rapid read out and verification of operating data in said main memory module, said network involving a central processing module having a central processor with a high speed processor data bus connecting a microcode RAM and data path array, said system comprising:
Dependencies are inferred from the claim text.