Apparatus and method for recovering a clock signal which is embedded in an incoming data stream

A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of:

• providing the incoming data stream to a data sampler circuit;
• operating the data sampler circuit to select one of a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;
• generating a recovered clock signal based on the selected clock phase;
• retiming the incoming data stream based on the recovered clock signal;
• and
• disabling operation of the data sampler circuit;
• wherein the operating step includes the step of strobing a plurality of flip-flops of the data sampler circuit with the incoming data stream to produce the selected clock phase;
• and wherein the operating step further includes the step of initiating the disabling step with the selected clock phase produced in the strobing step.

A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of:

• providing the incoming data stream and a plurality of clock phases to a data sampler circuit;
• first operating the data sampler circuit to select one of the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;
• generating a recovered clock signal based on the selected clock phase;
• second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal;
• and
• disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode.

A method of recovering a clock signal which is embedded in an incoming data stream, comprising the steps of:

• providing the incoming data stream to a data sampler circuit;
• first operating the data sampler circuit to select one of a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;
• generating a recovered clock signal based on the selected clock phase;
• second operating a retiming circuit in a normal data tracking mode to retime the incoming data stream based on the recovered clock signal;
• and
• disabling operation of the data sampler circuit while the retiming circuit is operating in the normal data tracking mode;
• wherein the first operating step includes the step of strobing a plurality of flip-flops of the data sampler circuit with the incoming data stream to produce the selected clock phase;
• and wherein the operating step further includes the step of initiating the disabling step with the selected clock phase produced in the strobing step.

An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising:

• a data sampler circuit for selecting a clock phase indicative of the embedded clock signal;
• a clock multiplexer for generating a recovered clock signal based on the selected clock phase;
• a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal;
• a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer;
• and
• means for disabling said data sampler circuit while said digital phase-locked loop circuit is operating in a normal data tracking mode.

An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising:

• a data sampler circuit for selecting a clock phase indicative of the embedded clock signal;
• a clock multiplexer for generating a recovered clock signal based on the selected clock phase;
• a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal;
• and
• a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer.

An apparatus for recovering a clock signal which is embedded in an incoming data stream having an analog phase-locked loop circuit and a digital phase-locked loop circuit coupled together, said digital phase-locked loop circuit comprising:

• a data sampler circuit for selecting a clock phase indicative of the embedded clock signal;
• a clock multiplexer for generating a recovered clock signal based on the selected clock phase;
• a lead/lag phase detector circuit coupled to the clock multiplexer for retiming the incoming data stream based the recovered clock signal;
• and
• a loop filter circuit coupled to said lead/lag phase detector circuit and said clock multiplexer;
• wherein said data sampler circuit includes a feedback circuit for disabling said data sampler circuit in response to selection of the clock phase indicative of the embedded clock signal.

An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising:

• means for selecting a clock phase from a plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;
• means for generating a recovered clock signal based on the selected clock phase;
• means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode;
• and
• means for disabling said selecting means while said retiming means is operating in the normal data tracking mode, wherein said disabling means includes a feedback circuit which is coupled to said selecting means and said retiming means.

An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising:

• means for generating a plurality of clock phases;
• means for selecting a clock phase from the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;
• means for generating a recovered clock signal based on the selected clock phase;
• and
• means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode, wherein said retiming means includes a lead/lag phase detector circuit coupled to said selecting means.

An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising:

• means for generating a recovered clock signal based on the selected clock phase;
• means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode;
• means for disabling said selecting means while said retiming means is operating in the normal data tracking mode;
• and
• a five-stage voltage controlled oscillator for generating the plurality of clock phases, wherein the plurality of clock phases is ten clock phases.

An apparatus for recovering a clock signal which is embedded in an incoming data stream, comprising:

• means for generating a plurality of clock phases;
• means for selecting a clock phase from the plurality of clock phases, the selected clock phase being indicative of the embedded clock signal;
• means for generating a recovered clock signal based on the selected clock phase;
• means for retiming the incoming data stream based on the recovered clock signal in a normal data tracking mode;
• and
• means for disabling said selecting means while said retiming means is operating in the normal data tracking