US 5,850,419 AGranted

Time diversity communication method and communication device

AssigneeNEC Corporation

InventorToshiya Todoroki

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Abstract

In time diversity communication system, loss of data or generation of incorrect data may occur due to, for example, the shadow effect. In the present invention, on the transmission side, an interlaced signal is generated in which the input digital signal string is combined with the same signal string delayed by n bits, k redundancy bits are added to every m bits of this signal, the signal is divided into blocks of (m+k) bits, an interleaving process is executed for every j blocks in which unique words are added, following which the signal is transmitted. On the receiving side, unique words are detected, a de-interleaving process is performed, and a check is made for the presence of error signals. The delayed and non-delayed signals are next separated from the decoded data, and depending on the state of the signals, the desired signal is selected at selector 33 and outputted. A conformity judgment circuit judges conformity with the separated signal determined to be effective using effective gate signals indicating the effectiveness or ineffectiveness of decoded data, performs switching control of the separated signals, and monitors synchronization.

Claims9

Dependent claims

A time diversity communication method comprising on a sending side:

a step for producing an interlaced signal by interlacing a non-delayed signal, which is a signal inputted at a current time, with a delayed signal that is a signal inputted n bits before said non-delayed signal and is delayed n bits;
a step for encoding by dividing said interlaced signal every m bits (where m<n), and adding k redundancy bits to each block of m bits;
a step for executing an interleaving process for each block of (m+k).times.j bits of encoded signal string and adding a unique word;
and
a step for first modulating and amplifying said interleaved signal string which has undergone said interleaving and addition of unique words, and then sending said modulated and amplified interleaved signal string as a transmission signal at a higher bit rate than that of the input signal;
and comprising on a receiving side:
a step for demodulating a received signal and storing said demodulated received signal within a buffer at a regeneration clock;
a step for reading out data stored in said buffer at a prescribed clock, executing de-interleaving, and producing a signal string of continuous (m+k).times.j -bit blocks;
a step for monitoring phase of said unique words within a data string when reading out stored data from said buffer, and correcting read-out addresses from said buffer upon detection of disparity in phase of unique words;
a step for decoding said signal string, which has been de-interleaved, using said redundancy bits to judge effectiveness at every m bits of said interlaced signal to which said redundancy bits are added, and outputting effective gate signals that indicate either effectiveness or ineffectiveness in accordance with this judgment and a decoded interlaced signal from which the redundancy bits have been eliminated;
a step for separating said non-delayed signal and said delayed signal from said decoded interlaced signal, and simultaneously, separating said effective gate signal corresponding to each of said non-delayed signal and said delayed signal;
a step for delaying by n bits each of said separated non-delayed signal and said effective gate signal corresponding to said non-delayed signal;
and
a step for, provided that said non-delayed signal that has been delayed n bits is signal (a), said delayed signal that has been separated is signal (b), said effective gate signal that has been delayed n bits is signal (c), and the effective gate signal corresponding to said signal (b) is signal (d), and moreover, a state in which signal (a) and signal (b) continuously match is considered to be a synchronized state, monitoring effectiveness or ineffectiveness of signal (a) and signal (b) based on the states of signal (c) and signal (d), respectively;
judging whether or not signal (b) is in a synchronized state with signal (a), both signals being determined as effective;
and selecting an output signal.

13 more elements

A time diversity communication device comprising:

an encoder that produces an interlaced signal by interlacing a non-delayed signal, which is a signal inputted at a current time, with a delayed signal that is a signal inputted n bits before said non-delayed signal and is delayed n bits;
a transmission channel encoder that encodes by dividing said interlaced signal every m bits (where m<n), and adding k redundancy bits to each block of m bits;
an interleaver that executes an interleaving process for each block of (m+k).times.j bits of an encoded signal string and adds a unique word;
and
transmitting means that modulates and amplifies an interleaved signal string outputted by said interleaver, and then sends said signal string as a transmission signal;
receiving means that receives a transmission signal, amplifies and demodulates said received signal, and generates a demodulated received signal;
a buffer for storing a demodulated received signal according to a regeneration clock;
reading means for reading out data stored in said buffer according to an external clock;
phase control means that detects unique words within a data string read out from said buffer, and controls read-out addresses of data from the buffer such that phase of unique words is kept uniform;
a de-interleaver that executes de-interleaving of data strings read out from said buffer, and outputs a signal string in continuous blocks of (m+k).times.j bits;
a transmission channel decoder that uses redundancy bits to judge effectiveness of each m bits of said interlaced signal to which said redundancy bits have been added of a signal string outputted from said de-interleaver, and that outputs in parallel effective gate signals that indicate either effectiveness or ineffectiveness in accordance with this judgment and a decoded interlaced signal from which said redundancy bits have been eliminated;
a first serial-parallel converter that separates said non-delayed signal and said delayed signal from said decoded interlaced signal;
a second serial-parallel converter that, in synchronism with said first serial-parallel converter, separates said effective gate signals corresponding to said non-delayed signals and said delayed signals, respectively;
first delay means that delays by n bits said non-delayed signal separated by said first serial-parallel converter;
second delay means that delays by n bits effective gate signals corresponding to said non-delayed signals separated by said second serial-parallel converter;
third delay means that confers a delay of a prescribed number of bits to said non-delayed signal (a) outputted by said first delay means, and fourth delay means that confer a delay of a prescribed number of bits to said delayed signal (b) separated by said first serial-parallel converter;
a selector that selects one of said output signals (a) and (b) outputted from said third and fourth delay means, respectively, and outputs the selected signal to the outside as a demodulated signal;
a conformity judgment circuit that inputs said non-delayed signal (a) and said delayed signal (b) from said first delay means and said first serial-parallel converter, respectively;
inputs effective gate signal (c) corresponding to said non-delayed signal (a) and effective gate signal (d) corresponding to said delayed signal (b) from said second delay means and said second serial-parallel converter, respectively;
monitors whether said signals (a, b) are effective or ineffective based on states of said signals (c, d);
detects whether said signal (b) matches said signal (a), both signals being determined as effective;
judges synchronization or non-synchronization between said signals (a, b) based on whether a counted number of continuous matches exceeds or does not reach a prescribed number;
and gives selection commands to said selector based on judgment results.

20 more elements

Dependencies are inferred from the claim text.