Fault block detecting system using abnormal current
AssigneeNEC Corporation
InventorMasaru Sanada
Life of this patent
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Abstract
In a semiconductor device formed by a plurality of logic blocks, a plurality of functional test patterns are generated and transmitted to the semiconductor device, and it is determined whether an abnormal current flows through the semiconductor device. When an abnormal current is detected, a fault block is determined in accordance with a table for storing the functional test patterns and the logic blocks operated by the functional test patterns.
Claims14
A system for detecting a fault block in a semiconductor device formed by a plurality of logic blocks, comprising:
- a table means for storing a relationship between a plurality of functional test patterns and operable logic blocks among said logic blocks operated on by said plurality of functional test patterns;
- means for sequentially generating said plurality of functional test patterns and transmitting said plurality of functional test patterns to said semiconductor device;
- means for detecting whether a current, produced by said plurality of functional test patterns and flowing through said semiconductor device, is larger than a certain value;
- means for determining whether said semiconductor device is switched from normal to abnormal in accordance with the current detected by said means for detecting;
- a first transition block extracting means for extracting transition blocks from among said operable logic blocks in accordance with said table means each time said semiconductor device is switched from normal to abnormal;
- and
- a fault block extracting means for extracting at least one common block as said fault block from among a plurality of groups of said transition blocks extracted by said first transition block extracting means.
A system for detecting a fault block in a semiconductor device formed by a plurality of logic blocks, comprising:
- a table means for storing a relationship between a plurality of functional test patterns and said logic blocks operated on by said plurality of functional test patterns;
- means for sequentially generating said plurality of functional test patterns and transmitting said plurality of functional test patterns to said semiconductor device;
- means for detecting whether a current, produced by said plurality of functional test patterns and flowing through said semiconductor device, is larger than a certain value;
- means for determining whether said semiconductor device is switched from normal to abnormal in accordance with the current detected by said means for detecting;
- a first transition block extracting means for extracting first transition blocks from among said logic blocks in accordance with said table means when said semiconductor device is switched from normal to abnormal for a first time;
- and
- a second transition block extracting means for extracting non-transition blocks from among said logic blocks in accordance with said table means when said semiconductor device is switched from normal to abnormal after said first transition block extracting means extracts said first transition blocks,
- said second transition block extracting means excluding said non-transition blocks from said first transition blocks, to obtain said fault block in said first transition blocks.
A system for detecting a fault block in a semiconductor device formed by a plurality of logic blocks, comprising:
- a table means for storing a relationship between a plurality of functional test patterns and said logic blocks operated on by said Plurality of functional test patterns;
- means for sequentially generating said plurality of functional test patterns and transmitting said plurality of functional test patterns to said semiconductor device;
- means for detecting whether a current, produced by said plurality of functional test patterns and flowing through said semiconductor device, is larger than a certain value;
- means for determining whether said semiconductor device is switched from normal to abnormal in accordance with the current detected by said means for detecting;
- a first transition block extracting means for extracting first transition blocks from among said logic blocks in accordance with said table means when said semiconductor device is switched from abnormal to normal for a first time;
- and
- a second transition block extracting means for extracting non-transition blocks from among said logic blocks in accordance with said table means when said semiconductor device is switched from abnormal to normal after said first transition block extracting means extracts said first transition blocks,
- said second transition block extracting means excluding said non-transition blocks among said first transition blocks, to obtain said fault block in said first transition blocks.
A method for detecting a faulty logic block in a plurality of logic blocks in a semiconductor, said method comprising the steps of:
- (a) storing a relationship between a plurality of functional test patterns and sets of the plurality of logic blocks, wherein the relationship defines which set of the plurality of logic blocks each of the plurality of functional test patterns actually tests;
- (b) generating one of the plurality of test patterns to test a corresponding set of the plurality of logic blocks;
- (c) detecting an output current of the semiconductor caused by the one of the plurality of test patterns;
- (d) determining if said output current is above a threshold value;
- (e) extracting the set of the plurality of logic blocks if a predetermined relationship between the output current and the threshold value is met;
- (f) returning to step (b) until all of the plurality of teat patterns are generated;
- (g) extracting at least one common logic block from all of the extracted sets of the plurality of logic blocks, as the faulty logic block.
Dependencies are inferred from the claim text.