Burst EDO memory address counter

A memory device comprising a plurality of addressable memory elements, the memory device fuirther comprising:

• a three bit address generation circuit adapted to receive a first memory address in response to a transition of an address latch signal, and further adapted to generate three least significant bits in a series of memory addresses in a selectable one of a plurality of predetermined burst address sequences in response to subsequent transitions of the address latch signal, the three bit address generation circuit comprising,
• a latch circuit for latching most significant bits in the first memory address,
• three one-bit counter circuits for incrementing the three least significant bits,
• a control circuit for controlling the three one-bit counter circuits, and
• a comparator circuit for comparing the first memory address with the series of memory addresses.

A method of performing a burst access of a memory device, comprising:

• loading a burst address counter with a first initial address;
• accessing a first memory element at the first initial address;
• advancing two least significant bits of the first initial address using the burst address counter;
• accessing a second memory element at an address provided by the burst address counter;
• comparing the first initial address with the address provided by the burst address counter;
• and
• terminating the burst access in response to a match of the first initial address with the address provided by the burst address counter.

A data processing system comprising:

• a microprocessor;
• and
• a memory controller coupled to the microprocessor and a memory device;
• the memory device comprising a plurality of addressable memory elements, the memory device further comprising:
• an address counter adapted to receive a first memory address from the memory controller in response to a transition of an address latch signal, and further adapted to generate a series of memory addresses in a selectable one of a plurality of predetermined burst address sequences in response to subsequent transitions of the address latch signal.