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US 5,850,367 AGranted
Static type semiconductor memory with latch circuit amplifying read data read on a sub bit line pair and transferring the amplified read data to a main bit line pair and operation method thereof
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTomohisa Wada, Yoshiyuki Haraguchi
Life of this patent
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Abstract
A static type semiconductor memory device includes a main bit line pair, and a plurality of memory blocks connected to the main bit line pair. Each of the memory blocks includes a local bit line pair, a static memory connected to the local bit line pair, an amplifier which amplifies potential difference between the paired local bit lines, and a data transfer gate which transfers data between the local bit line pair and the main bit line pair.
Claims8
A static type semiconductor memory device comprising:
- a plurality of main bit line pairs;
- a plurality of word lines;
- and
- a plurality of memory blocks connected to one of said plurality of main bit line pairs, each of said plurality of memory blocks including
- a sub bit line pair substantially parallel to said main bit line pairs,
- a static memory cell connected to said sub bit line pair and one of said plurality of word lines,
- an amplifier amplifying potential difference between said paired sub bit lines, and
- a data transfer gate transferring data between said sub bit line pair and one of said plurality of main bit line pairs;
- wherein
- said static memory includes two driver transistors of a first conductivity type, and
- said amplifier includes only two transistors,
- a first transistor of a second conductivity type having its source, drain and gate respectively connected to a first power supply node, one sub bit line of said sub bit line pair, and the other of said sub bit line pair, and
- a second transistor of the second conductivity type having its source, drain and gate respectively connected to a second power supply node, the gate of said first transistor, and the drain of said first transistor.
10 more elements
A static type semiconductor memory device comprising:
- a plurality of main bit line pairs;
- a plurality of word lines;
- and
- a plurality of memory blocks connected to one of said plurality of main bit line pairs, each of said plurality of memory blocks including
- a sub bit line pair,
- a static memory cell connected to said sub bit line pair and one of said plurality of word lines,
- an amplifier amplifying potential difference between said paired sub bit lines, and
- a data transfer gate transferring data between said sub bit line pair and one of said plurality of main bit line pairs;
- wherein
- at least two of said plurality of memory blocks are placed between one pair of said plurality of main bit line pairs, and arranged in a direction orthogonally crossing said plurality of main bit line pairs.
7 more elements
A method of operating a static type semiconductor memory device including:
- a plurality of main bit line pairs;
- a plurality of word lines;
- and
- a plurality of memory blocks connected to one of said plurality of main bit line pairs, each of said plurality of memory blocks including
- a sub bit line pair substantially parallel to said main bit line pairs,
- a static memory cell connected to said sub bit line pair and one of said plurality of word lines,
- an amplifier amplifying potential difference between said paired sub bit lines, and
- a data transfer gate transferring data between said sub bit line pair and one of said plurality of main bit line pairs, wherein
- said static memory includes two driver transistors of a first conductivity type, and
- said amplifier includes only two transistors,
- a first transistor of a second conductivity type having its source, drain and gate respectively connected to a first power supply node, one sub bit line of said sub bit line pair, and the other of said sub bit line pair, and
- a second transistor of the second conductivity type having its source, drain and gate respectively connected to a second power supply node, the gate of said first transistor, and the drain of said first transistor,
- the method comprising the steps of:
- equalizing potentials of one of said plurality of main bit line pairs and said sub bit line pair;
- selecting one of said plurality of word lines;
- amplifying data read onto said sub bit line pair from said static memory cell connected to the selected one of said plurality of word lines;
- and
- transferring said amplified data from said sub bit line pair to one of said main bit line pairs.
15 more elements
A method of operating a static type semiconductor memory device including:
- a plurality of main bit line pairs;
- a plurality of word lines;
- and
- a plurality of memory blocks connected to one of said plurality of main bit line pairs, each of said plurality of memory blocks including
- a sub bit line pair substantially parallel to said main bit line pairs,
- a static memory cell connected to said sub bit line pair and one of said plurality of word lines,
- an amplifier amplifying potential difference between said paired sub bit lines, and
- a data transfer gate transferring data between said sub bit line pair and one of said plurality of main bit line pairs, wherein
- said static memory includes two driver transistors of a first conductivity type, and
- said amplifier includes only two transistors,
- a first transistor of a second conductivity type having its source, drain and gate respectively connected to a first power supply node, one sub bit line of said sub bit line pair, and the other of said sub bit line pair, and
- a second transistor of the second conductivity type having its source, drain and gate respectively connected to a second power supply node, the gate of said first transistor, and the drain of said first transistor,
- said method comprising the steps of:
- equalizing potentials of one of said plurality of main bit line pairs and said sub bit line pair;
- selecting one of said plurality of word lines;
- amplifying data read onto said sub bit line pair from said static memory cell connected to the selected one of said plurality of word lines;
- transferring said amplified data from said sub bit line pair to one of said plurality of main bit line pairs;
- providing write data to one of said plurality of main bit line pairs;
- transferring the write data from one of said plurality of main bit line pairs to said sub bit line pair by said data transfer gate;
- and
- storing the write data of said sub bit line pair in said static memory cell.
18 more elements
Dependencies are inferred from the claim text.