Memory array having dummy cells implemented using standard array cells

A DRAM memory array implemented by an integrated circuit, the DRAM memory array comprising:

• a bank of standard array cells arranged in rows and columns, comprising:
• a plurality of rows of array cells, the array cells operable to provide memory storage;
• and
• a plurality of rows of dummy cells, the dummy cells operable to provide a reference voltage level;
• a row decode block coupled to the bank of standard array cells via a plurality of wordlines, the wordlines comprising array cell wordlines and dummy cell wordlines;
• a sense amplifier block coupled to the bank of standard array cells via a plurality of bitlines, the sense amplifier block comprising a plurality of sense amplifiers coupled to the bitlines;
• an array counter electrode coupled to each array cell;
• and
• a dummy cell counter electrode coupled to each dummy cell, the dummy cell counter electrode allowing discrimination level control of the dummy cells;
• the DRAM memory array operable to charge the plurality of dummy cells to a precharge voltage level during a bitline precharge period such that the dummy cells operate to provide a reference voltage and capacitive balance to the sense amplifiers when sensing an array cell, and further operable to adjust a voltage level of the dummy cell counter electrode after wordline strobe to allow discrimination level control.

A method for constructing a memory array in an integrated circuit, comprising:

• forming a bank of standard array cells arranged in rows and columns such that the standard array cells include a plurality of rows of array cells operable to provide memory storage and includes a plurality of rows of dummy cells operable to provide a reference voltage level;
• connecting a row decode block to the bank of standard array cells via a plurality of wordlines where the wordlines comprise array cell wordlines and dummy cell wordlines;
• connecting a sense amplifier block to the bank of standard array cells via a plurality of bitlines where the sense amplifier block es a plurality of sense amplifiers coupled to the bitlines;
• and
• charging the plurality of dummy cells to a precharge voltage level during a bitline precharge period such that the dummy cells provide a reference voltage and capacitive balance to the sense amplifiers when sensing an array cell.