US 5,850,365 AGranted

Sense amplifier with individually optimized high and low power modes

AssigneeAltera Corporation

InventorsDirk A. Reese, Myron W. Wong, John C. Costello

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Abstract

The present invention is a sense amplifier circuit for use with programmable logic devices that provides improved switching time by actively limiting the voltage swing on the bit line which it is sensing, rather than passively sensing the voltage, employs feedback circuits to further improve switching time and may be selectively operated in low power mode without significant reduction in switching speed. Voltage reference control circuitry, comprising variable current limiters controlled by the potential of a supply of reference potential, can be added to improve noise immunity. The circuitry of the supply of reference potential is designed so that its sensitivity to fabrication variations is substantially similar to that of the sense amplifier and so that it adjusts the reference potential accordingly.

Claims27

Dependent claims

A memory comprising:

a memory cell;
a first node coupled to the memory cell, the first node configured to move, depending on the state of the memory cell, to either a first voltage or a second voltage when the memory cell is accessed, and to the first voltage when the memory cell is not accessed;
a second node coupled to the first node, the second node configured to assume, depending on the state of the memory cell, either a first state or a second state when the memory cell is accessed, and configured to assume the first state when the memory cell is not accessed;
and
a recovery circuit configured to reset the second node from the second state to the first state when the second node assumes the second state after the memory cell is accessed the recovery circuit including:
a first transition element configured to transition the second node from the second state to the first state when the first node moves to a first intermediate voltage between the first voltage and the second voltage;
and
a second transition element configured to transition the second node from the second state to the first state when the first node moves to a second intermediate voltage between the first voltage and the second voltage, wherein the second transition element is configured to be activated prior to the activation of the first transition element.

5 more elements

A memory comprising:

a memory cell;
a first node coupled to the memory cell, the first node configured to move, depending on the state of the memory cell, to either a first voltage or a second voltage when the memory cell is accessed, and to the first voltage when the memory cell is not accessed;
a second node coupled to the first node, the second node configured to assume, depending on the state of the memory cell, either a first state or a second state when the memory cell is accessed, and configured to assume the first state when the memory cell is not accessed;
and
a recovery circuit configured to reset the second node from the second state to the first state when the second node assumes the second state after the memory cell is accessed, the recovery circuit including:
a first transition element configured to transition the second node from the second state to the first state when the first node moves to a first intermediate voltage between the first voltage and the second voltage;
a second transition element configured to transition the second node from the second state to the first state when the first node moves to a second intermediate voltage between the first voltage and the second voltage;
a fifth transition element configured to selectively couple the second node to a source of potential;
and
a sixth transition element controlled by the voltage at the output node and configured to selectively couple a third node to a source of potential.

7 more elements

Dependencies are inferred from the claim text.