Programmable memory with single bit encoding
AssigneeSGS-Thomson Microelectronics S.A.
InventorLuigi Pascucci
Life of this patent
Estimating the term…
Abstract
A coding device including an array of multibit registers, each being composed of a plurality of programmable nonvolatile memory cells connected to an OR configuration to a common sensing line of the register to which a single reading circuit is associated. A first, select/enable bus (SELbus) controls the connection of only one at a time of said programmable memory cells to said common sensing line of each multibit register. To each wire of a second, configuring bus (CODE bus) are connected in common the current terminals of as many programming transistors as the memory cells that compose each register, and to each wire of a third, contingently programming bus (PG bus) are connected the gates of the programming transistors of memory cells of the same order of said registers.
Claims15
A coding device comprising an array of multibit registers each composed of a plurality of programmable nonvolatile memory cells characterized in that:
- said programmable elementary cells of each register are functionally connected in an OR configuration to a common sensing line of the multibit register, and including programming transistors having current terminals and gates;
- a single reading circuit is associated to each multibit register and has an input connected to said common sensing line;
- said device further comprising a first select/enable bus for connecting a single elementary programmable cell of the same order of each multibit register at one time to said common sensing line of the respective register;
- a second configuring bus to each wire of which are connected the current terminals of the programming transistors of all programmable elementary cells that compose each register;
- a third contingent programming bus, to each wire of which are connected the gates of the programming transistors of the memory cells of the same order of said registers.
A fuse encoding structure comprising:
- at least one programmable nonvolatile memory element;
- a programming transistor functionally connected in series with said nonvolatile memory elements;
- a select-enable transistor functionally connected in series with said nonvolatile memory element and in parallel with said programming transistor;
- and
- a common programming circuit operatively connected to said programming transistor and said nonvolatile memory element for controlling said programming transistor and nonvolatile memory element.
A coding method comprising the steps of:
- forming an array of multibit registers each composed of a plurality of programmable nonvolatile memory cells;
- functionally connecting said programmable elementary cells of each register in an OR configuration to a common sensing line of the multibit register;
- associating a single reading circuit to each multibit register that has an input connected to the common sensing line;
- connecting a first select/enable bus to single elementary programmable cell of the same order of each multibit register at one time to the common sensing line of the respective register;
- connecting each wire of a second configuring bus to the current terminals of the programming transistors of all programmable elementary cells that compose each register;
- and
- connecting each wire of a third contingent programming bus to the gates of the programming transistors of the memory cells of the same order of the registers.
Dependencies are inferred from the claim text.