Calculating 2A+ sign(A) in a single instruction cycle
AssigneeSamsung Semiconductor, Inc.
InventorRoney S. Wong
Life of this patent
Estimating the term…
Abstract
The expression 2A+sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementing A, bit-complementing (A+A+2) when A is less than zero, bit-complementing (A+A+1) when A is equal to zero, and bit-complementing all bits except a least significant bit of (A+A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+A+1) and a second carry-out bit from (A+A+2) have different logical values. In this manner, 2A+sign(A) can be calculated by a general purpose computer in a single instruction cycle.
Claims11
An apparatus for calculating 2A+sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, comprising:
- a first inverter circuit for bit-complementing A to obtain A;
- a data selector circuit for setting a constant C to two when A is less than zero and setting the constant C to one when A is greater than or equal to zero;
- an adder circuit for calculating (A+A+2) at a sum output when A is less than zero, and for calculating (A+A+1) at the sum output when A is greater than or equal to zero;
- a second inverter circuit for bit-complementing the sum output;
- and
- a multiplexer for selecting between a least significant bit of an output of the second inverter circuit and a least significant bit of the sum output, wherein an output of the second inverter circuit with the least significant bit thereof replaced by an output of the multiplexer provides 2A+sign(A).
An apparatus for calculating 2A+sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, comprising:
- a first inverter circuit having an operand input coupled to A and having an output for providing a bit-complement of A;
- a data selector circuit coupled to a sign bit of A and having an output for setting a constant C to one when A is greater than or equal to zero and for setting the constant C to two when A is less than zero;
- an adder circuit having first and second operand inputs coupled to the output of the first inverter circuit, having a third operand input coupled to the output of the data selector circuit, and having a sum output representing a sum of the first, second and third operands;
- a second inverter circuit having an operand input coupled to the sum output and having an output for providing a bit-complement of the sum output;
- a zero detect circuit for determining whether A is zero or nonzero;
- a multiplexer having a first input coupled to a least significant bit of the output of the second inverter circuit, having a second input coupled to a least significant bit of the sum output, and having a select input;
- and
- a control circuit, responsive to the sign bit of A and the zero detect circuit, having a control output coupled to the select input of the multiplexer, which causes the multiplexer to select the first input thereof when A is less than or equal to zero, and causes the multiplexer to select the second input thereof when A is greater than zero;
- wherein the output of the second inverter circuit with the least significant bit thereof replaced by an output of the multiplexer provides 2A+sign(A).
Dependencies are inferred from the claim text.