Digital FM demodulator using pulse generators

A method for demodulating an input FM signal comprising the steps:

• generating a pulse in a pulse output signal responsive to an edge of the input FM signal such that a frequency of pulses in the pulse output signal corresponds to a frequency of the input FM signal;
• and
• low pass filtering the pulse output signal to generate a demodulated signal having a magnitude corresponding to the frequency of the input FM signal;
• wherein the step of generating a pulse in a pulse output signal further comprises:
• generating a pulse in a first pulse signal responsive to a rising edge of the input FM signal,
• generating a pulse in a second pulse signal corresponding to a falling edge of the input FM signal, and
• combining the first and second pulse signals to form the pulse output signal;
• and
• wherein the step of generating a pulse in a first pulse signal further comprises
• clocking a first flip-flop with the input FM signal,
• latching an output of the first flip-flop in a second flip-flop clocked by a clock signal,
• clearing the first flip-flop with an output of the second flip-flop,
• latching an output of the second flip-flop in a third flip-flop clocked by an inverted clock signal,
• clearing the second flip-flop with an output of the third flip-flop,
• feeding back an inverted output of the third flip-flop to an input of the first flip-flop, and
• clearing the third flip-flop when an inverted output of the third flip-flop and the inverted clock signal are both logic low;
• and
• wherein the step of generating a pulse in a second pulse signal further comprises
• inverting the input FM signal,
• clocking a fourth flip-flop with the inverted input FM signal,
• latching an output of the fourth flip-flop in a fifth flip-flop clocked by the clock signal,
• clearing the fourth flip-flop with an output of the fifth flip-flop,
• latching an output of the fifth flip-flop in a sixth flip-flop clocked by an inverted clock signal,
• clearing the fifth flip-flop with an output of the sixth flip-flop,
• feeding back an inverted output of the sixth flip-flop to an input of the fourth flip-flop, and
• clearing the sixth flip-flop when an inverted output of the sixth flip-flop and the inverted clock signal are both logic low;
• and
• wherein the step of combining the first and second pulse signals to form the pulse output signal further comprises performing a NAND function on an inverted output of the second flip-flop and an inverted output of the fifth flip-flop to produce the pulse output signal.