High and low speed output buffer with controlled slew rate

Abstract

An output buffer is provided which receives an input signal for output onto an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage corresponding to a logic value of the input signal. The second driver has a higher driving capacity than the first driver. The output buffer also has control circuitry receiving a transition in logic value of the input signal and at least one mode signal. The control circuitry responds to the transition in logic value by delaying the second driver from driving the output terminal to a complementary voltage until after the first driver begins to drive the output terminal to the complementary voltage. In so doing, the control circuitry delays the second driver by a first delay, when the mode signal(s) indicates a full speed mode. On the other hand, the control circuitry delays the second driver by a second delay, that is longer than the first delay, when the mode signal(s) indicates a low speed mode.

Dependencies are inferred from the claim text.