Actively regulated totem pole TTL output stage

A TTL output stage for driving a load, comprising:

• a differentially-connected pair of transistors for receiving a differential input signal;
• first and second output transistors coupled to respectively source current to and sink current from said load wherein said first output transistor is responsive to a first one of said differentially-connected pair;
• a level-shift circuit that couples said second output transistor to a second one of said differentially-connected pair;
• a diode;
• a pull-down resistor wherein said diode and said pull-down resistor are coupled across said second output transistor to respectively set high and low signal levels;
• and
• a control transistor coupled across said second output transistor and further coupled to said second one of said differentially-coupled pair, said control transistor thereby coupled to compare a signal across said load to a signal of said level-shift circuit and, in response, to draw current from said second one of said differentially-coupled pair when necessary to hold said second output transistor out of saturation and on the edge of conduction.

A TTL output stage for driving a load, comprising:

• a supply voltage terminal;
• an output terminal for connection to a load;
• a ground terminal;
• a first npn output transistor having a base, a collector that is connected to the supply voltage terminal, and an emitter that is connected to the output terminal;
• a second npn output transistor having a base, a collector that is connected to the output terminal, and an emitter that is connected to the ground terminal;
• a driver circuit comprising a pair of differentially connected npn transistors having collectors that are respectively connected to first and second drive terminals on one side of first and second pull-up resistors, the other sides of which are connected to the supply voltage terminal, emitters that are connected to the ground terminal, and bases that respond to a differential input signal to generate first and second complementary drive voltage signals at the first and second drive terminals, respectively, that switch between low and high drive levels;
• a buffer circuit that is connected between the first drive terminal and the base of the first npn output transistor to buffer the driver circuit so that a) when the first drive voltage signal switches from the low to the high drive level, the first transistor draws transient current from the supply voltage terminal and supplies it to the output terminal to switch the load to a high load voltage level, and b) when the first drive voltage switches from the high to the low drive level the first transistor is turned off;
• a bias circuit that is connected between the second drive terminal and the base of the second npn output transistor to clamp and level shift the second drive voltage signal's high drive level to provide a reference voltage at an internal terminal and to provide a drive voltage at the base of the second transistor that is approximately a fully-on diode voltage so that a) when the second drive voltage signal switches from the low to the high drive level, sufficient base current is driven into the second transistor's base to turn it on such that it sinks transient current from the load and returns it to the ground terminal thereby switching the load to a low load voltage level, and b) when the second drive voltage signal switches from the high to the low drive level, the second transistor is turned off;
• and
• an npn regulation transistor having a base that is connected to the bias circuit's internal terminal, a collector that is connected to the second drive terminal, and an emitter that is connected to the output terminal to sense the load voltage such that when the load voltage falls to approximately a diode voltage below the reference voltage at its base the regulation transistor turns on thereby drawing current from the supply voltage terminal through the second pull-up resistor such that the second drive voltage signal's high drive level is reduced thereby reducing the drive voltage at the base of the second output transistor so that it is held near the edge of conduction whereby a) the second output transistor does not saturate when the load voltage is driven from the high to the low load voltage level thereby reducing the level of steady state current in the output stage and b) the second transistor is turned off before the first transistor is turned on when the load voltage is driven from the low to the high load voltage level thereby reducing the amount of transient current that does not interact with the load.