Low voltage swing circuits for low power clock distribution and methods of using the same
AssigneeIntel Corporation
InventorsQing K. Zhu, Michael Zhang
Life of this patent
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Abstract
A clock distribution system for low power operation. Such a clock distribution system includes a global clock generation circuit coupled to generate a global clock signal. This global clock signal is received by a local clock generation circuit which generates a local clock signal. While the system has an operating voltage generally used throughout the system, at least one of the global clock signal and the local clock signal is a small swing clock signal which has a voltage swing substantially less than the operating voltage of the system.
Claims26
A clock distribution system having an operating voltage for providing clocks to a circuit operating at the operating voltage, comprising:
- a global clock generation circuit coupled to generate a global clock signal which has a voltage swing substantially less than said operating voltage;
- and
- a local clock generation circuit coupled to receive said global clock signal, said local clock generation circuit having a comparator for comparing a common mode voltage supply and said global clock signal, the local clock generation circuit being coupled to generate a local clock.
A clock generation system operating at a source voltage established relative to a ground voltage, the clock generation system comprising:
- a CLK1 clock signal line having an associated first capacitance;
- a CLK1# clock signal line having an associated second capacitance;
- a CLK2 clock signal line having an associated third capacitance;
- a CLK2# clock signal line having an associated fourth capacitance;
- a first clock generation circuit having a charge sharing mechanism selectably coupling said CLK1 clock signal line to said CLK1# clock signal line to produce an intermediate voltage, said intermediate voltage being between the operating voltage and the ground voltage and determined by said first capacitance and said second capacitance;
- and
- a second clock generation circuit having a second charge sharing mechanism selectably coupling said CLK2 clock signal line to said CLK2# clock signal line to produce a second intermediate voltage, said second intermediate voltage being between the operating voltage and the ground voltage and determined by said third capacitance and said fourth capacitance.
A method of distributing clock signals, comprising the steps of:
- receiving an input clock signal;
- generating a plurality of clock signals having a voltage swing substantially less than an operating voltage by utilizing charge sharing on pairs of complementary clock lines during a first phase;
- and
- driving the plurality of clock signals to a plurality of two phase small swing compatible elements.
A signal distribution system, comprising:
- a generation circuit coupled to receive an input signal and to generate an output signal having a voltage swing substantially less than an operating voltage;
- a local regeneration circuit comparator having a first input coupled to said global clock signal and a second input coupled to a common mode voltage supply, the local regeneration circuit being coupled to receive said output signal, the local regeneration circuit having a full swing local output signal.
A method of distributing a clock signal, comprising the steps of:
- receiving an input clock signal having a first voltage swing;
- generating a global clock signal having a voltage swing substantially less than said first voltage swing;
- and
- generating a local clock signal having the first voltage swing using a comparator having a first input coupled to receive the global clock signal and a second input biased using a common mode voltage.
A clock generation system operating at a source voltage established relative to a ground voltage, the clock generation system comprising:
- a first clock signal line having an associated first capacitance;
- a second clock signal line having an associated second capacitance;
- a clock generation circuit having a charge sharing mechanism coupling said first clock signal line to said second clock signal line to produce an intermediate voltage during a first clock phase, said intermediate voltage being between the operating voltage and the ground voltage and determined by said first capacitance and said second capacitance, the clock generation circuit driving the first clock signal line to the source voltage during a second clock phase and driving second clock signal line to the ground voltage during the second clock phase.
Dependencies are inferred from the claim text.