Data transmission method and data transmission circuit

A semiconductor integrated circuit included in a first electronic device which is coupled to a second electronic device via a clock signal line and a bus line, said bus line being terminated via a terminating resistor having one end coupled to the bus line and another end applied with a terminating voltage, said semiconductor integrated circuit comprising:

• a data output terminal coupled to the bus line;
• a circuit generating a clock signal and outputting the clock signal to the clock signal line;
• and
• an output control circuit setting said date output terminal to a high impedance when the clock signal indicates an inactive state so that a state where data is output to the bus line and a state where an impedance between the first electronic device and the bus line is set to a high impedance is alternately repeated within one cycle of the clock signal.

A data transmission method for exchanging data between at least first and second electronic devices which are coupled via a plurality of bus lines, each of the bus lines being terminated via a terminating resistor having one end coupled to a respective bus line and another end applied with a terminating voltage, said data transmission method comprising the steps of:

• (a) setting a high logic level of data to a voltage higher than the terminating voltage and setting a low logic level of the data to a voltage lower than the terminating voltage;
• (b) continuously outputting the data from the first electronic device to at least one bus line at a timing determined by a first clock signal by alternately repeating a state where the data is output to said at least one bus line and a state where an impedance between the first electronic device and said at least one bus line is set to high impedance;
• and
• (c) exchanging the first clock signal between the first and second electronic devices via a clock signal line which is terminated via a terminating resistor having one end coupled to the clock signal line and another end applied with the terminating voltage.

A data transmission method for exchanging data between at least first and second electronic devices which are coupled via a plurality of bus lines, each of the bus lines being terminated via a terminating resistor having one end coupled to a respective bus line and another end applied with a terminating voltage, said data transmission method comprising the steps of:

• (a) setting a high logic level of data to a voltage higher than the terminating voltage and setting a low logic level of the data to a voltage lower than the terminating voltage;
• (b) continuously outputting the data from the first electronic device to at least one bus line at a timing determined by a first clock signal by alternately repeating a state where the data is output to said at least one bus line and a state where an impedance between the first electronic device and said at least one bus line is set to high impedance;
• and
• (c) continuously inputting the data from said at least one bus line to the second electronic device at a timing determined by a second clock signal by alternately repeating a state where the data is input from said at least one bus line and a state where no data is input from said at least one bus line
• wherein said first clock signal and said second clock signal are synchronized.

A data transmission circuit for exchanging data between at least first and second electronic devices which are coupled via a plurality of bus lines, each of the bus lines being terminated via a terminating resistor having one end coupled to a respective bus line and another end applied with a terminating voltage, said data transmission circuit comprising:

• means for setting a high logic level of data to a voltage higher than the terminating voltage and setting a low logic level of the data to a voltage lower than the terminating voltage;
• means, provided in the first electronic device, for continuously outputting the data from the first electronic device to at least one bus line at a timing determined by a first clock signal by alternately repeating a state where the data is output to said at least one bus line and a state where an impedance between the first electronic device and said at least one bus line is set to a high impedance;
• and
• means for exchanging the first clock signal between the first and second electronic devices via a clock signal line which is terminated via a terminating resistor having one end coupled to the clock signal line and another end applied with the terminating voltage.

A data transmission circuit for exchanging data between at least first and second electronic devices which are coupled via a plurality of bus lines, each of the bus lines being terminated via a terminating resistor having one end coupled to a respective bus line and another end applied with a terminating voltage, said data transmission circuit comprising:

• means for setting a high logic level of data to a voltage higher than the terminating voltage and setting a low logic level of the data to a voltage lower than the terminating voltage;
• means, provided in the first electronic device, for continuously outputting the data from the first electronic device to at least one bus line at a timing determined by a first clock signal by alternately repeating a state where the data is output to said at least one bus line and a state where an impedance between the first electronic device and said at least one bus line is set to a high impedance;
• and
• means, provided in the second electronic device, for continuously inputting the data from said at least one bus line to the second electronic device at a timing determined by a second clock signal by alternately repeating a state where the data is input from said at least one bus line and a state where no data is input from said at least one bus line
• wherein said first clock signal and said second clock signal are synchronized.