Programmable logic array integrated circuit devices

A programmable logic array integrated circuit device comprising:

• a plurality of programmable logic modules, each of which is programmable to perform any of a plurality of logic functions on signals applied to said logic module, and each of which includes a register for registering a signal associated with said logic module, said register have a clear input terminal and being cleared by a predetermined signal applied to said clear input terminal;
• a clear input pin associated with the plurality of programmable logic modules;
• a clear conductor extending from said clear input pin adjacent to each of said logic modules;
• a programmable logic connector associated with the plurality of programmable logic modules for programmably connecting the clear input pin to the clear conductor when a global clear mode of operation is desired;
• and
• a clear control circuit associated with each of the registers in the plurality of programmable logic modules for operatively connecting said clear input terminal of the associated register to said clear conductor when said global clear mode of operation is selected, thereby allowing all of said registers to be cleared by an appropriate signal applied to said clear input pin.

A programmable logic module for a programmable logic array integrated circuit device comprising:

• programmable logic circuitry for performing any of a plurality of logic functions on a plurality of input signals applied to said logic circuitry in order to produce an output signal of said logic circuitry;
• a flip-flop circuit for registering a signal applied to a data input terminal of said flip-flop circuit in response to a clock signal applied to a clock input terminal of said flip-flop circuit to produce a registered output signal of said flip-flop circuit;
• and
• switch circuitry for selectively applying either the output signal of said logic circuitry or the registered output signal of said flip-flop circuit to said data input terminal of said flip-flop circuit depending on the states of first and second control signals applied to said switch circuitry, said switch circuitry responding to a first state of said first control signal by always connecting said output signal of said logic circuitry to said data input terminal of said flip-flop circuit regardless of the state of said second control signal, and said switch circuitry responding to a second state of said first control signal by connecting said output signal of said logic circuitry to said data input terminal of said flip-flop circuit in response to a first state of said second control signal and by connecting said registered output signal of said flip-flop circuit to said data input terminal of said flip-flop circuit in response to a second state of said second control signal.