US 5,850,151 A · Programmable logic array intergrated circuit devices

Abstract

A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

Claims16

Dependent claims

An input/output cell for a programmable logic array integrated circuit comprising:

an input/output pin for use in connecting said programmable logic array integrated circuit to external circuitry;
an input terminal for enabling said input/output cell to receive a signal from other portions of said programmable logic array integrated circuit;
an output terminal for enabling said input/output cell to output a signal to other portions of said programmable logic array integrated circuit;
a register circuit for registering a signal applied to a data input port of said register circuit in response to a clock signal applied to said register circuit in order to produce a registered output signal of said register circuit;
a first programmable switch for applying either a signal applied to said input/output pin without registration between said input/output pin and said input port or a signal applied to said input terminal to said input port;
a second programmable switch for applying said registered output signal to either one of said input/output pin and said output terminal without requiring said registered output signal to be applied to said input/output pin when said registered output signal is applied to said output terminal;
and
clock enable circuitry for selectively preventing said register circuit from responding to said clock signal.

5 more elements

A programmable logic array integrated circuit device comprising:

a plurality of input/output cells, each of which includes (1) an input/output pin for use in connecting said programmable logic array integrated circuit to external circuitry, and (2) a register circuit for selectively registering a data signal being passed through said input/output cell in either direction between said input/output pin and other portions of said device, said register circuit registering said data signal in response to a clock signal applied to a clock input terminal of said register circuit;
a plurality of clock input pins;
a plurality of clock conductors, each of which extends from a respective one of said clock input pins adjacent to each of said input/output cells;
and
a programmable switch associated with each of said input/output cells for programmably selecting any of said clock conductors as the source of a clock signal applied the clock input terminal of the register circuit in that input/output cell.

2 more elements

A programmable logic array integrated circuit device comprising:

programmable logic array circuitry which is programmable to produce a plurality of output signals;
a plurality of output pins for use in connecting said device to external circuitry;
an output driver circuit associated with each of said output pins, each of said output driver circuits being operable to selectively apply an associated first one of said output signals to the associated output pin when said output driver circuit is enabled by an output enable signal applied to an output enable terminal of said output driver circuit;
and
an output enable control circuit associated with each of said output driver circuits for applying an associated second one of said output signals to the output enable terminal of said output driver circuit, wherein said associated second one of said output signals is selected from said plurality of output signals such that each of said output driver circuits can be enabled by one of said output signals that is selectable by only one of said output control circuits.

2 more elements

Dependencies are inferred from the claim text.

Programmable logic array intergrated circuit devices

Life of this patent

Programmable logic array intergrated circuit devices

Life of this patent

Abstract

Claims16