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US 5,850,093 AGranted
Uni-directional flash device
OwnerHuang Chang Tarng, Min Ming Tarnginventors
Life of this patent
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Abstract
The flash device is a field effect single cell device. The flash device has the source laying under the gate. The variance of gate voltage has the direct capacitor coupling and current injecting effects with the source to speed up the response of circuit. Furthermore, the process of the flash device is comparable with the CMOS device. It is an ideal device for the output buffer which has the anti-ground-bounce and anti-power-droop capabilities. The single cell technology is applied to the single cell active pixel to integrate four different components into one cell. The versatile operation is applied to have the super-flash EEPROM.
Claims71
A semiconductor device(FIG. 21A) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second and third regions of second conductivity type in said first region, said third region being L shape region having a vertical segment and a horizontal segment, said second and said vertical segment of said third regions each adjoining said major surface, said third region being spaced from said second region by a portion of said first region, said horizontal segment of said third region buried inside said first region and under said major surface,
- a gate electrode insulatingly overlaying a portion of said first region and right above the buried horizontal segment of said third region,
- a drain electrode connected to said second region and a source electrode connected to said third region,
- said second region having a portion laying under said gate, said vertical segment of said third region being away from said gate to have a single-side offset with said gate to form a surface drainage to drain carriers to elinimate electric shield formed by carriers that electric field of said gate being able to reach bulk portion of said first semiconductor region to form a bulk channel(FIG. 23A and FIG. 23B), but said third region having the buried horizontal segment laying directly under said gate,
- whereby said structure forms a field effect transistor with said gate controlling the a buried portion and an interface between said buried portion and a channel portion, said channel portion of said first region being formed under the applied voltage of said gate to allow current flowing only from the buried portion of said third region to said second region.
3 more elements
A semiconductor device(FIG. 22) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second and third regions of second conductivity type in said first region, said third region having a vertical segment and a horizontal segment, said second and said vertical segment of said third regions each adjoining said major surface, said horizontal segment of said third region buried inside said first region and under said major surface,
- a gate electrode insulatingly overlaying a portion of said first region and right above the buried horizontal segment of said third region,
- a drain electrode connected to said second region and a source electrode connected to said third region,
- whereby said structure forms a field effect transistor with said gate controlling the potential barrier at the interface of said first region and said buried portion of said third region, a channel portion of said first region being formed under the applied voltage of said gate to allow current flowing from the buried portion of said third region to said second region,
- said second region and said vertical segment of said third region which adjoining said major surface being aligned with edges of said gate, a small portion of said first region having higher doping concentration than a concentration of said first region to have higher threshold voltage than a threshold voltage of said first region, said small portion laying under said gate to prevent current flowing directly from said drain to said source through said surface channel.
3 more elements
A semiconductor device(FIG. 21E) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second and third regions of second conductivity type in said first region, said second and third regions being L shape regions having a vertical segment and a horizontal segment respectively, said vertical segment of-second region and said vertical segment of said third region each adjoining said major surface, said third region being spaced from said second region by a portion of said first region, said horizontal segment of said third region and said horizontal segment of said third region buried inside said first region and under said major surface,
- a gate electrode insulatingly overlaying a portion of said first region and right above the buried horizontal segment of said third region,
- a drain electrode connected to said second region and a source electrode connected to said third region,
- said second region having a horizontal segment laying under said gate, said vertical segment of said third region being away from said gate, said third region having the horizontal segment laying under said gate,
- whereby said structure forms a field effect transistor with said gate controlling the potential barrier at the interface of said first region and said buried portion of said third region, having field induced bipolar effect, a channel portion of said first region being formed under the applied voltage of said gate to allow current flowing from the buried horizontal segment of said third region to said second region.
3 more elements
A semiconductor device(FIG. 22E) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second and third regions of second conductivity type in said first region, said second region having a vertical segment and a horizontal segment, said third region having a vertical segment and a horizontal segment, said vertical segment of said second region and said vertical segment of said third region each adjoining said major surface, said horizontal segments of said second region and third region buried inside said first region and under said major surface,
- a gate electrode insulatingly overlaying a portion of said first region and right above the buried horizontal segments of said second region and third region,
- a drain electrode connected to said second region and a source electrode connected to said third region,
- whereby said structure forms a field effect transistor with said gate controlling the potential barrier at the interface of said first region and said buried portion of said third region, having field induced bipolar effect, a channel portion of said first region being formed under the applied voltage of said gate to allow current flowing from the buried segment of said third region to said second region,
- said vertical segment of second region and said vertical segment of said third region which adjoining said major surface being aligned with edges of said gate, a small portion of said first region having higher doping concentration than a concentration of said first region to have higher threshold voltage than a threshold voltage of said first region, said small portion laying under said gate to prevent current flowing directly from said drain to said source through said surface channel.
3 more elements
A semiconductor device(FIG. 21A) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second and third regions of second conductivity type in said first region, said third region being L shape region having a vertical segment and a horizontal segment, said second and said vertical segment of said third regions each adjoining said major surface, said third region being spaced from said second region by a portion of said first region, said horizontal segment of said third region buried inside said first region and under said major surface,
- a gate electrode insulatingly overlaying a portion of said first region and right above the buried horizontal segment of said third region,
- an ohmic contact adjoining said major surface being beneath said gate;
- a drain electrode connected to said second region and a source electrode connected to said third region,
- said second region having a portion laying under said gate, said vertical segment of said third region being away from said gate but having the buried horizontal segment laying under said gate,
- whereby said structure forms a field effect transistor with said gate controlling the potential barrier at the interface of said first region and said buried portion of said third region, a channel portion of said first region being formed under the applied voltage of said gate to allow current flowing from the buried portion of said third region to said second region.
4 more elements
A semiconductor device(FIG. 22) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second and third regions of second conductivity type in said first region, said third region having a vertical segment and a horizontal segment, said second and said vertical segment of said third regions each adjoining said major surface, said horizontal segment of said third region buried inside said first region and under said major surface,
- a gate electrode insulatingly overlaying a portion of said first region and right above the buried horizontal segment of said third region,
- an ohmic contact adjoining said major surface being beneath said gate;
- a drain electrode connected to said second region and a source electrode connected to said third region,
- whereby said structure forms a field effect transistor with said gate controlling the potential barrier at the interface of said first region and said buried portion of said third region, a channel portion of said first region being formed under the applied voltage of said gate to allow current flowing from the buried portion of said third region to said second region,
- said second region and said vertical segment of said third region which adjoining said major surface being aligned with edges of said gate, a small portion of said first region having higher doping concentration than a concentration of said first region to have higher threshold voltage than a threshold voltage of said first region, said small portion laying under said gate to prevent current flowing directly from said drain to said source through said surface channel.
4 more elements
A semiconductor device(FIG. 21E) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second and third regions of second conductivity type in said first region, said second and third regions being L shape regions having a vertical segment and a horizontal segment respectively, said vertical segment of-second region and said vertical segment of said third region each adjoining said major surface, said third region being spaced from said second region by a portion of said first region, said horizontal segment of said third region and said horizontal segment of said third region buried inside said first region and under said major surface,
- a gate electrode insu.atingly overlaying a portion of said first region and right above the buried horizontal segment of said third region,
- an ohmic contact adjoining said major surface being beneath said gate;
- a drain electrode connected to said second region and a source electrode connected to said third region,
- said second region having a horizontal segment laying under said gate, said vertical segment of said third region being away from said gate, said third region having the horizontal segment laying under said gate,
- whereby said structure forms a field effect transistor with said gate controlling the potential barrier at the interface of said first region and said buried portion of said third region, having field induced bipolar effect, a channel portion of said first region being formed under the applied voltage of said gate to allow current flowing from the buried horizontal segment of said third region to said second region.
4 more elements
A semiconductor device(FIG. 22E) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second and third regions of second conductivity type in said first region, said second region having a vertical segment and a horizontal segment, said third region having a vertical segment and a horizontal segment, said vertical segment of said second region and said vertical segment of said third region each adjoining said major surface, said horizontal segments of said second region and third region buried inside said first region and under said major surface,
- a gate electrode insulatingly overlaying a portion of said first region and right above the buried horizontal segments of said second region and third region,
- an ohmic contact adjoining said major surface being beneath said gate;
- a drain electrode connected to said second region and a source electrode connected to said third region,
- whereby said structure forms a field effect transistor with said gate controlling the potential barrier at the interface of said first region and said buried portion of said third region, having field induced bipolar effect, a channel portion of said first region being formed under the applied voltage of said gate to allow current flowing from the buried segment of said third region to said second region,
- said vertical segment of second region and said vertical segment of said third region which adjoining said major surface being aligned with edges of said gate, a small portion of said first region having higher doping concentration than a concentration of said first region to have higher threshold voltage than a threshold voltage of said first region, said small portion laying under said gate to prevent current flowing directly from said drain to said source through said surface channel.
4 more elements
A semiconductor device(FIG. 21E) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second and third regions of second conductivity type in said first region, said second region adjoining said major surface, said third region being spaced from said second region by a portion of said first region, said third region being buried inside said first region and under said major surface,
- a gate electrode insulatingly overlaying a portion of said first region and right above the buried fourth region,
- an ohmic contact adjoining said major surface being beneath said gate;
- a drain electrode connected to said second region and a source electrode connected to said third region,
- whereby said structure forms a field effect transistor with said gate controlling the potential barrier at the interface of said first region and said buried portion of said third region, a channel portion of said first region being formed under the applied voltage of said gate to allow current flowing from the third region to said second region.
3 more elements
A semiconductor device(FIG. 22E) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second, third and fourth regions of second conductivity type in said first region, said second region and fourth region adjoining said major surface, said third region being buried inside said first region and under said major surface,
- a gate electrode insulatingly overlaying a portion of said first region and right above the buried third region,
- an ohmic contact adjoining said major surface being beneath said gate;
- whereby said structure forms a field effect transistor with said gate controlling the potential barrier at the interface of said first region and said third region, a channel portion of said first region being formed under the applied voltage of said gate to allow current flowing from the third region to said second region,
- said second region and said vertical segment of said third region which adjoining said major surface being aligned with edges of said gate, a small portion of said first region having higher doping concentration than a concentration of said first region to have higher threshold voltage than a threshold voltage of said first region, said small portion laying under said gate to prevent current flowing directly from said fourth region to said second region through said surface channel.
3 more elements
A single cell semiconductor device(FIG. 21H) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second and third regions of second conductivity type in said first region, said second and third region being L shape region having a vertical segment and a horizontal segment, a drain electrode connected to said second region and a source electrode connected to said third region,
- a fourth semiconductor region of second conductivity which having a flat upper portion locating between said second and third region, said fourth region each adjoining said major surface, a switching capacitor gate electrode insulatingly overlaying said fourth region;
- a precharging gate overlaying between said second region and said fourth region, a channel portion of said first region being formed under a applied voltage of said precharging gate to allow current flowing from said second region to said fourth region, a junction between said fourth region and said first region constituting a reverse diode;
- a fifth isolation region beneath said fourth semiconductor contacting with said fourth region, said fourth region, fifth region, horizontal segments of said second and third regions constituting a field transistor.
2 more elements
A semiconductor device(FIG. 30L and FIG. 30U) comprising:
- a first semiconductor region of first conductivity type, said first semiconductor region having a major surface;
- second and third regions of second conductivity type in said first region, said third region being spaced from said second region by a portion of said first region,
- a gate electrode insulatingly overlaying a portion of said first region,
- a drain electrode connected to said second region and a source electrode connected to said third region,
- a floating gate underlying said gate electrode and insulated from said first, second and third regions, said gate electrode being a control gate,
- a low resistance connection means connecting said first conductivity region to switching voltage to inducing charge separation in said floating gate;
- local high field strength needle pin mechanisms transferring charges through insulation layer between said floating gate and control gate.
4 more elements
Dependencies are inferred from the claim text.