FLASH-EPROM with embedded EEPROM

An integrated circuit comprising:

• a p-type semiconductor substrate comprising a p-well region isolated by a region of deep n-well according to a triple well structure;
• at least a first array of FLASH-EPROM memory cells and at least a second array of EEPROM memory cells, the EEPROM memory cells being formed in said p-well region, all of said memory cells comprising a semiconductor and a floating gate capacitively coupled within an active area to a channel region of the semiconductor through a gate oxide, only the EEPROM cells of said second array comprising a further window of capacitive coupling in the active area of the memory cell between the semiconductor and the same floating gate through a tunnel oxide which is thinner than said gate oxide;
• at least a charge pump circuit capable of supplying high voltages for programming and erasing said memory cells;
• and
• auxiliary circuitry for accessing said memory cells for reading, writing or programming and erasing them, erase access being byte-selectable in said second array of memory cells but not in said first array of memory cells, said auxiliary circuitry comprising transistors destined to function at a relatively low voltage and transistors destined to function at the high voltages during the erasing and programming phases;
• the capacitive coupling between the floating gate and a channel region of the semiconductor in the active area of each FLASH-EPROM memory cell being established through a first dielectric oxide layer of a thickness that can be independently optimized;
• the capacitive coupling between the floating gate and a semiconductor channel region in the active area of the transistors destined to function at the high voltages being established through a second dielectric oxide layer of a greater thickness than said first dielectric layer;
• the capacitive coupling through said window in the active area of each of said EEPROM memory cells being established through a third oxide dielectric layer whose thickness is less than that of said first dielectric layer;
• said transistors destined to function at the relatively low voltage having a gate dielectric comprising a fourth dielectric oxide layer, grown simultaneously with but to a smaller thickness than said third dielectric oxide layer;
• the capacitive coupling between the floating gate of each EEPROM memory cell with a respective control gate structure being established onto a relatively thick field oxide layer adjacent to the active area of the cell.