Semiconductor memory device and method of reading a data therefrom

A semiconductor memory device comprising:

• word lines which are arranged in a row direction:
• bit lines which are arranged in a column direction while intersecting said word lines;
• a plurality of memory elements each having a gate electrode formed on a channel forming region through an insulating layer between a source region and a drain region, said memory elements being arranged in the form of a matrix at intersecting points of said word lines and said bit lines, in which the source regions and the drain regions are formed in said channel forming region while being spaced apart from each other;
• and
• source lines arranged in the column direction orthogonal to said word lines and connected to the source regions of said memory elements, wherein
• said gate electrodes are connected to said word lines;
• said drain regions are connected to said bit lines;
• and said source lines belonging to nonselected columns are reverse biased with respect to said channel forming region.

A semiconductor memory device comprising:

• word lines which are arranged in a row direction;
• bit lines which are arranged in a column direction while intersecting said word lines;
• a plurality of memory elements each having a gate electrode formed on a channel forming region through an insulating layer between a source region and a drain region, said memory elements arranged in the form of a matrix at intersecting points of said word lines and said bit lines, in which said gate electrodes are connected to said word lines and said drain regions are connected to said bit lines;
• source lines arranged in the row direction parallel to said word lines and connected to the source regions of said memory elements;
• and
• a source line driving means for driving said source lines by an inverted signal of said word lines.

A semiconductor memory device comprising:

• word lines which are arranged in a row direction;
• bit lines which are arranged in a column direction while intersecting said word lines;
• a plurality of memory elements each having a gate electrode formed on a channel forming region through an insulating layer between a source region and a drain region, said memory elements being arranged in the form of a matrix at intersecting points of said word lines and said bit lines, in which said gate electrodes are connected to said word lines and said drain regions are connected to said bit lines;
• source lines arranged in the row direction parallel to said word lines and connected to the source regions of said memory elements,
• a serial circuit of a switching means and a constant potential drop means connected between said source line and a reference potential for every row of said memory array, which becomes conductive only at the reading of the data;
• and
• a source line driving means for driving said source lines by an inverted signal of said word lines.

A semiconductor memory device comprising:

• word lines;
• bit lines intersecting said word lines;
• a plurality of source lines;
• and
• a plurality of memory elements, said memory elements having at least:
• a semiconductor channel-forming region;
• a source region and a drain region spaced apart from each other and contacting said channel-forming region;
• an intermediate layer on the surface of said channel-forming region sandwiched between said source and drain regions, said intermediate layer comprising at least an insulator and a charge storing means in or on said insulator;
• and a conductive gate on said intermediate layer;
• wherein said conductive gates are connected to said word lines, and said drain regions are connected to said bit lines;
• said source regions are connected to said source lines, and said source lines are connected to a plurality of reverse bias means, said reverse bias means supplying to said source lines a reverse bias with respect to said channel-forming region.

A method of reading a semiconductor memory device, where the device comprises:

• word lines bit lines;
• bit lines intersecting said word lines;
• a plurality of source lines;
• a plurality of memory elements, said memory elements having at least a semiconductor channel-forming region;
• a source region and a drain region spaced apart from each other and contacting said channel-forming region;
• an intermediate layer on a surface of said channel-forming region sandwiched between said source and drain regions, said intermediate layer comprising at least an insulator and a charge storing means in or on said insulator;
• and a conductive gate on said intermediate layer, said conductive gates are connected to said word lines;
• said drain regions are connected to said bit lines;
• and said source regions are connected to said source lines;
• the method comprising:
• reverse-biasing said source regions with respect to said channel-forming region using said source lines;
• applying a read selection signal to at least one of said conductive gates through one of said word lines;
• and
• reading as an electric current between said drain and source regions of a memory element an amount of stored charge in a memory element having a conductive gate to which said read selection signal is applied.

A semiconductor memory device comprising:

• word lines;
• bit lines intersecting said word lines;
• a common source line;
• and
• a plurality of memory elements, each of said memory elements comprising:
• a semiconductor channel-forming region;
• a source region and a drain region spaced apart from each other and contacting said channel-forming region;
• an intermediate layer on a surface of said channel-forming region sandwiched between said source and drain regions, said intermediate layer comprising an insulator and a charge storing means in or on said insulator;
• and a conductive gate on said intermediate layer;
• wherein said conductive gates are connected to said word lines;
• said drain regions are connected to said bit lines;
• said source regions are connected to said common source line;
• said common source line is connected to a reverse bias means, said reverse bias means supplying to said common source line a reverse bias with respect to said channel-forming region.

A method of reading a semiconductor memory device, where the device comprises:

• word lines;
• bit lines intersecting said word lines;
• a common source line;
• a plurality of memory elements, each of said memory elements comprising:
• a semiconductor channel-forming region;
• a source region and a drain region spaced apart from each other and contacting said channel-forming region;
• an intermediate layer on a surface of said channel-forming region sandwiched between said source and drain regions, said intermediate layer comprising an insulator and a charge storing means in or on said insulator;
• and a conductive gate on said intermediate layer;
• wherein said conductive gates are connected to said word lines;
• said drain regions are connected to said bit lines;
• and said source regions are connected to said common source line;
• the method comprising:
• reverse-biasing said source regions with respect to said channel-forming region using said source line;
• applying a read selection signal to at least one of said conductive gates through one of said word lines;
• and
• reading as an electric current between said drain and source regions of a memory element an amount of stored charge in a memory element having a conductive gate to which said read selection signal is applied.

A semiconductor memory device comprising:

• word lines which are arranged in a row direction;
• bit lines which are arranged in a column direction while intersecting said word lines;
• a plurality of memory elements each having a gate electrode formed through an insulating layer on a channel forming region between a source region and a drain region, said memory elements being arranged in the form of a matrix at intersecting points of said word lines and said bit lines, wherein the source regions and the drain regions are formed in said channel forming region and spaced apart from each other;
• and
• source lines arranged in the row direction parallel to said word lines and connected to the source electrodes of said memory elements, wherein
• said gate electrodes are connected to said word lines;
• said drain electrodes are connected to said bit lines;
• and said source lines belonging to nonselected rows are reverse biased with respect to said channel forming region.