Method and structure for isolating semiconductor devices after transistor formation
AssigneeAdvanced Micro Devices, Inc.
InventorsMark I. Gardner, Fred N. Hause, H. Jim Fulford, Jr.
Life of this patent
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Abstract
A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.
Claims18
A method of fabricating a semiconductor device, comprising:
- providing a semiconductor substrate, an upper region of said semiconductor substrate having laterally displaced source/drain regions and channel regions including a common source/drain region laterally displaced between a first channel region and a second channel region;
- forming a first and a second gate structure on said semiconductor substrate over said first and second channel regions respectively;
- introducing a first concentration of a first impurity into said common source/drain region, wherein said first concentration of said first impurity substantially resides above a first depth below an upper surface of said semiconductor substrate;
- introducing a second concentration of a second impurity into said common source/drain region, wherein said second concentration of said second impurity substantially resides above a second depth greater than said first depth below an upper surface of said semiconductor substrate;
- subsequent to said introducing said first and second impurities into said common source/drain region, forming a trench in said semiconductor substrate wherein said trench is laterally displaced within said common source/drain region and wherein a floor of said trench is situated at a third depth greater than said second depth below said upper surface of said semiconductor substrate;
- depositing a trench dielectric material within said trench and upon upper surfaces of said first and second gate structures such that said common source/drain region is divided into electrically isolated first and second source/drain regions;
- and
- planarizing portions of said trench dielectric material extending above said first and second gate structures and said trench.
A method for isolating semiconductor devices, comprising:
- providing a semiconductor substrate, wherein said semiconductor substrate includes laterally displaced source/drain regions and channel regions;
- forming laterally displaced first and second transistors partially within said semiconductor substrate, wherein said first and second transistors have a common source/drain region and wherein said first and second transistors comprise first and second gate structures, respectively, having sidewalls substantially perpendicular to an upper surface of said semiconductor substrate;
- forming an isolation trench through said common source/drain region;
- depositing a trench dielectric material within said trench and upon upper surfaces of said transistors such that said common source/drain region is divided into electrically isolated first and second source/drain regions to electrically isolate said first transistor from said second transistor;
- and
- planarizing said trench dielectric extending above said first and second transistors and said trench.
Dependencies are inferred from the claim text.