Method for fabricating a nested capacitor

A method for fabricating a capacitor on a semiconductor substrate, comprising the steps of:

• forming a first TEOS layer over said semiconductor substrate;
• forming a polysilicon layer over said first TEOS layer;
• forming a second TEOS layer over said polysilicon layer;
• removing a portion of said second TEOS layer to form a window therein, thereby exposing a portion of the polysilicon layer;
• forming a first dielectric spacer in said window;
• removing the exposed portion of the polysilicon layer in the window, thereby exposing a portion of said first TEOS layer;
• removing said second TEOS layer and the exposed portion of said first TEOS layer, thereby forming a trench extending down to the semiconductor substrate;
• depositing a polysilicon plug in the trench and forming a first polysilicon spacer around said first dielectric spacer;
• forming a second dielectric spacer around said first polysilicon spacer;
• forming a second polysilicon spacer around said second dielectric spacer;
• removing the first dielectric spacer and the second dielectric spacer, thereby forming a lower electrode including said polysilicon plug, said polysilicon layer, said first polysilicon spacer and said second polysilicon spacer;
• forming a dielectric layer over said lower electrode;
• and
• forming an upper electrode over said dielectric layer.

A method for fabricating a capacitor on a semiconductor substrate, comprising the steps of:

• forming a first TEOS layer over said semiconductor substrate;
• forming a polysilicon layer over said first TEOS layer;
• forming a second TEOS layer over said polysilicon layer;
• removing a portion of said second TEOS layer to form a window therein, thereby exposing a portion of the polysilicon layer;
• forming a first dielectric spacer in said window;
• removing the exposed portion of the polysilicon layer in the window, thereby exposing a portion of said first TEOS layer;
• removing said second TEOS layer and the exposed portion of said first TEOS layer, thereby forming a trench extending down to the semiconductor substrate;
• depositing a polysilicon plug in the trench and forming a first polysilicon spacer around said first dielectric spacer;
• forming in alternating layers at least one further dielectric spacer and at least one further polysilicon spacer around said first polysilicon spacer;
• removing the first dielectric spacer and each said further dielectric spacer, thereby forming a lower electrode including said polysilicon plug, said polysilicon layer, said first polysilicon spacer and each said further polysilicon spacer;
• forming a dielectric layer over said lower electrode;
• and
• forming an upper electrode over said dielectric layer.