Method of manufacturing a semiconductor device

A method of manufacturing a complementary MOSFET semiconductor device including a field effect transistor circuit, which method comprises:

• forming a plurality of gate electrodes on respective surfaces of a plurality of active regions of a semiconductor substrate provided with p-type and n-type regions with gate insulating films interposed therebetween, including at least a first gate electrode of an NMOS transistor formed on a p-type region and a second gate electrode of a PMOS transistor formed on an n-type region, each of said NMOS and PMOS transistors comprising source and drain regions, and each source and drain region of each of said transistors comprising a first impurity region and a second impurity region having an impurity concentration greater than that of said first impurity region;
• forming sidewall spacers on respective sidewalls of said plurality of gate electrodes by performing a plurality of depositions of oxide insulating films including at least one simultaneous deposition of an oxide insulating film on said plurality of gate electrodes including said first and second gate electrodes, and anisotropically etching a plurality of times, wherein the number of insulating layers and sidewall spacers formed on said second gate electrode are greater than those formed on said first gate electrode;
• and
• implanting n-type impurity ions and p-type impurity ions into said p-type and n-type regions respectively using either said first and second gate electrodes or both of said first and second gate electrodes and said sidewall spacers as masks, thereby forming source and drain regions,
• said implanting impurity ions carried out by covering said active region provided with said p-type region with a resist film at least once, thereby making the offset of the source and drain regions of said NMOS formed in said p-type region smaller than that of said source and drain regions of said PMOS formed in said n-type region.