A method for concurrently fabricating bipolar transistors and field effect transistors (FETs) on a silicon substrate comprising the steps of:
- forming a silicon oxide layer on a principal surface of said silicon substrate thereby forming a pad oxide layer;
- depositing a silicon nitride layer on said pad oxide layer thereby providing an oxidation barrier layer;
- patterning said silicon nitride layer and forming silicon nitride stripes over bipolar transistor device areas having respective decreasing widths for emitter, base, and collector regions of said bipolar transistors, and patterning said silicon nitride layer over FET device areas having silicon nitride stripes of decreasing widths, one silicon nitride stripe for forming a source area, and a narrower silicon nitride stripe for forming a gate electrode/drain area for each of said field effect transistors;
- thermally oxidizing said silicon substrate and forming a field oxide isolation around said device areas having said silicon nitride stripes;
- and concurrently by the same oxidation,
- laterally oxidizing said substrate under said silicon nitride stripes over said bipolar transistor device areas to form a punchthrough oxide having a thickness that varies inversely as a function of the width of said silicon nitride stripes and provides a punchthrough oxide implant mask having self-aligned variable thicknesses for said bipolar transistors, and where said oxide implant mask over said collector is thinner than said field oxide isolation, said oxide implant mask over said base is thinner than said oxide implant mask over said collector, and said pad oxide over said emitter is thinner than said oxide implant mask over said base, where the width of said silicon nitride stripe for said emitter region is sufficiently wide to prevent said punchthrough oxide from forming, thereby retaining said pad oxide over said emitter region;
- and concurrently,
- laterally oxidizing said substrate under said silicon nitride stripes over said FET device areas to form a punchthrough oxide over said gate electrode/drain area while retaining said pad oxide over said source area, said punchthrough oxide self-aligned to said pad oxide;
- wet etching and removing said silicon nitride layer;
- forming a first photoresist implant block-out mask over said FET device areas;
- ion implanting consecutively said collector, base, and emitter for said bipolar transistors through said punchthrough oxide implant mask having said self-aligned variable thicknesses, wherein the ion energy for said implanting of said collector is sufficient to pass through said oxide implant mask over said collector regions into said silicon substrate and forms a buried collector under said base and said emitter regions in said substrate, and the ion energy for said implanting of said base is sufficient to pass through said oxide implant mask over said base region and to form a buried base under said emitter region, and further said emitter is implanted through said pad oxide into said silicon substrate over said buried base;
- stripping said first photoresist implant block-out mask;
- forming a second photoresist implant block-out mask over said bipolar transistor device areas;
- and
- removing said pad oxide on said FET device areas;
- implanting P-dopant shield regions in said FET device areas using said punchthrough oxide on said FET device areas and said field oxide as an implant block-out mask;
- etching said punchthrough oxide implant mask off said FET device areas;
- stripping said second photoresist mask;
- and
- forming an FET gate oxide on said FET device areas;
- depositing and patterning an N.sup.+ doped polysilicon layer, thereby forming FET gate electrodes on said gate oxide;
- ion implanting lightly doped source/drain areas;
- depositing and anisotropically plasma etching back an insulating layer thereby forming sidewall spacers on said FET gate electrodes;
- implanting N.sup.+ doped source/drain regions adjacent to said sidewall spacers on said FET gate electrodes, and thereby completing said bipolar transistors and said field effect transistors (FETs) for making BiFET and BiCMOS circuits.