Back to results
US 5,849,612 AGranted
MOS poly-si thin film transistor with a flattened channel interface and method of producing same
AssigneeSeiko Instruments Inc.
InventorsHiroshi Takahashi, Yoshikazu Kojima
Life of this patent
Estimating the term…
Abstract
A thin film field effect transistor has a three-layer structure including a polycrystalline semiconductor layer to be a channel region, a conductive layer to be a gate electrode and a insulating layer to be a gate insulating film between the channel region and the gate electrode. The roughness of an interface between the channel region and the gate insulating film is less than a few nm so that the current drivability of the transistor is improved.
Claims4
A method of producing a thin film field effect transistor comprising the steps of:
- forming, on a backing substrate, a polycrystalline semiconductor layer having a surface, the polycrystalline semiconductor layer having a first section defining a channel region and two further sections separated from one another by the first section;
- flattening the surface of the polycrystalline semiconductor layer at least at the first section;
- forming an insulating layer to define a gate insulating film on the flattened surface of the polycrystalline semiconductor layer;
- depositing a conductive layer to define a gate electrode on the gate insulating film;
- and
- introducing an impurity into the two further sections of the polycrystalline semiconductor layer to form source and drain regions which are separated from one another by the channel region.
3 more elements
Dependencies are inferred from the claim text.