Elemental titanium-free liner and fabrication process for inter-metal connections
AssigneeTexas Instruments Incorporated
InventorsGirish A. Dixit, Anthony J. Konecni
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AssigneeTexas Instruments Incorporated
InventorsGirish A. Dixit, Anthony J. Konecni
Estimating the term…
An elemental titanium-free liner and cavity cleansing process is provided that allows for the elimination of conventional sputter etch and elemental titanium depositions. A low power plasma etch provides for pre-conditioning/cleansing of cavities such as contacts and vias. A refractory metal is provided as a cavity liner. Preferably, the liner is comprised of several discrete refractory metal liner layers, each having a thickness of about 25-100 .ANG., that can be applied by CVD and/or PVD. A low power plasma cleanse is preferably interposed between each liner layer deposition. A suitable metal plug can be deposited and directed into the cavity to complete cavity filling. Preferably, the metal plug is an elemental aluminum or aluminum alloy plug that is deposited by CVD and force-filled into the cavity to reduce the incidence of micro-voids within the cavity. Elimination of the conventional sputter etch and the high temperature processing (temp..gtoreq..sup..about. 400.degree. C.) associated with such processing allows for the use of polymeric dielectrics, such as the family of polytetrafluorethylene ("PTFE") compounds, which exhibit a dielectric constant (.kappa.) of about 1.9; parylene (.kappa.=.sup..about. 2.2-2.6); aerogels and xerogels (.kappa.=.sup..about. 1.1-1.8); and the family of polymeric spin-on-glass ("SOG") materials; use of all the foregoing materials being attractive because of the ability of these materials to reduce parasitic capacitance of the interconnects. Because these polymeric materials are temperature sensitive, their use has been limited, as conventional device fabrication practices typically require operation temperatures far in excess of the melting and/or decomposition temperature for these materials.
A method for depositing a liner in a cavity formed in a semiconductor device, comprising the steps of:
Dependencies are inferred from the claim text.