Address protection circuit and method for preventing access to unauthorized address rangers

An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory in a system having a processor unit, the address protection circuit including:

• (a) a data storage means for storing at least one authorization code for a corresponding address range in the addressable memory,
• (b) a generating and transmitting means for generating and transmitting an access authorization signal to the addressable memory upon receipt from a requesting address source of a memory address request corresponding to a stored authorization code;
• and
• (c) a communication pathway coupled to the requesting address source and the protected addressable memory the communication pathway bypassing the processor unit and being adapted for communicating data between the requesting address source and the protected addressable memory in response to receipt of the access authorization signal by the addressable memory.

An address protection circuit for detecting erroneous memory address requests from at least one address source to an addressable memory, the address protection circuit including:

• (a) content addressable storage means,
• (1) for storing at least one authorization code for a corresponding address range in the addressable memory, and
• (2) for generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a regulating address source to enable the requesting address source to directly access the protected addressable memory;
• (b) programming means, coupled to the content addressable storage means, for selectively programming each authorization code within the content addressable storage means;
• wherein each memory address request includes at set of memory address signals and a source identification code identifying a requesting address source.

An address protection circuit for detecting erroneous memory address requests from at least one address source to an addressable memory in a system having a processor unit, the address protection circuit including:

• (a) a content addressable storage device for:
• (1) storing at least one authorization code for a corresponding address range in the addressable memory;
• and
• (2) generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a requesting address source;
• wherein each memory address request includes a set of memory address signals and a source identification code identifying a requesting address source;
• wherein a communication pathway is coupled to the requesting address source and the addressable memory such that the communication pathway bypasses the processing unit, and wherein the communication pathway communicates data between the requesting address source and the addressable memory.

An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:

• (a) content addressable random access memory means for:
• (1) storing at least one authorization code for a corresponding address range in the protected addressable memory;
• and
• (2) generating and transmitting an access authorization signal to the protected addressable memory upon receipt of a memory address request corresponding to one of the stored authorization codes from an address source to enable the requesting address source to directly access the protected addressable memory;
• (b) multiplexing means, coupled to the content addressable random access memory means, for selecting between two sets of input signals and coupling the selected set of input signals to the content addressable random access memory means;
• (c) first programmable array logic means, coupled to the content addressable random access memory means, for preventing access to the protected addressable memory when any one of the following conditions occur;
• (1) an address request is attempted at an address is outside a predetermined range of addresses;
• (2) a disable signal is asserted;
• or
• (3) the access authorization signal is not asserted,
• (d) second programmable array logic means, coupled to the first programmable array logic means, for generating and transmitting a content addressable random access memory write signal to the content addressable random access memory means, and the disable signal to the first programmable array logic means;
• (e) third programmable array logic means, coupled to the second programmable array logic means, for generating and transmitting to the content addressable random access memory means, a content addressable random access memory select signal upon detection by the third programmable array logic means of a predetermined key.

An address protection circuit for detecting erroneous memory address requests from at least one address source to an addressable memory, the address protection circuit including:

• (a) content addressable storage means:
• (1) for storing at least one authorization code for a corresponding address range in the addressable memory, and;
• (2) for generating and transmitting an access authorization signal to the addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a requesting address source;
• (b) means, coupled to the content addressable storage means, for transmitting the generated access authorization signal to the requesting address source upon receipt of a memory address request from the requesting address source;
• wherein each memory address request from the address source includes a set of memory address signals and a source identification code identifying a requesting address source.

An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:

• (a) content addressable storage means, coupled to at least one address source and to the protected addressable memory:
• (1) for storing at least one authorization code for a corresponding address range in the protected addressable memory;
• and
• (2) for generating and transmitting an access authorization signal to the protected addressable memory upon receipt of d memory address request corresponding to a stored authorization code from a requesting address source to enable the requesting address source to directly access the protected addressable memory;
• (b) programming means, coupled to the content addressable storage means for selectively programming each authorization code, and including a means for limiting access to the programming means to preselected address sources;
• and
• (c) disabling means, coupled to the content addressable storage means, for preventing the transmittal of the access authorization signal to the protected addressable memory;
• wherein each memory address request includes a set of addressable memory address signals, a source identification code identifying the requesting address source, and a signal selectively identifying a read or write operation.

A method for detecting erroneous memory address requests from at least one address source to an addressable memory in a system having a processor unit, comprising the steps of:

• (a) receiving memory address requests from a requesting address source;
• (b) generating and transmitting an access approval signal to the addressable memory upon receipt of a valid memory address request from the requesting address source,
• (c) receiving the access approval by the addressable memory;
• (d) communicating data between the requesting address source and the addressable memory;
• and
• (e) bypassing the processing unit when performing step (d).

A method for detecting erroneous memory address requests from at least one address source to an addressable memory in a system having a processor unit, comprising the steps of:

• (a) receiving memory address requests from at least one address source;
• (b) comparing each received memory address request to a set of predefined authorization codes corresponding to address ranges in the addressable memory a
• (c) generating and transmitting the access authorization signal to the addressable memory upon receipt of a memory address request corresponding to at least one of the predefined authorization codes,
• (d) receiving the access approval by the addressable memory;
• (e) communicating data between the requesting address source and the addressable memory and
• (f) bypassing the processing unit when performing step (e).

An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:

• (a) a content addressable random access memory for:
• (1) storing at least one authorization code for a corresponding address range in the protected addressable memory;
• and
• (2) generating and transmitting an access authorization signal to the protected addressable memory upon receipt of a memory address request corresponding to a stored authorization code from a requesting address source to enable the requesting address source to directly access the protected addressable memory;
• (b) a multiplexer, coupled to the content addressable random access memory, for selecting between two sets of input signals and coupling the selected set of input signals to the content addressable random access memory;
• (c) first programmable array logic circuit, coupled to the content addressable random access memory circuit, for preventing access to the protected addressable memory when any one of the following conditions occur:
• (1) an address request is attempted at an address outside a predetermined range of addresses;
• (2) a disable signal is asserted;
• or
• (3) the access authorization signal is not asserted,
• (d) second programmable array logic circuit, coupled to the first programmable array logic circuit, for generating and transmitting a content addressable random access memory write signal to the content addressable random access memory, and the disable signal to the first programmable array logic circuit;
• (e) third programmable array logic circuit, coupled to the second programmable array logic circuit, for generating and transmitting to the content addressable random access memory, a content addressable random access memory select signal upon detection by the third programmable array logic circuit of a predetermined key.

An address protection circuit for detecting erroneous memory address requests from at least one address source to a protected addressable memory, the address protection circuit including:

• (a) a content addressable storage device for:
• (1) storing at least one authorization code for a corresponding address range in the protected addressable memory;
• and
• (2) generating and transmitting an access authorization signal to the protected, addressable memory upon receipt of a memory address request corresponding to a stored authorization code to enable the requesting address source to directly access the protected addressable memory;
• (b) a programming circuit, coupled to the content addressable storage device, for selectively programming each authorization code, and including a security checking circuit for limiting access to the programming circuit to preselected address sources;
• and
• (c) a disabling circuit, coupled to the content addressable storage device, for preventing the transmittal of the access authorization signal to the protected addressable memory;
• wherein each memory address request from the address source includes a set of addressable memory address signals, a source identification code identifying a requesting address source, and a signal selectively identifying a read or write operation.

A method for detecting erroneous memory address requests from an address source to an addressable memory in a redundant computer system, comprising the steps of:

• receiving memory address requests from the address source;
• providing a predefined authorization code corresponding to an authorized address range for said address source in the addressable memory;
• and
• providing an access authorization signal to the addressable memory selectively according to said authorization code upon receipt of a memory address request from said address source.