Method and apparatus for caching state information within a directory-based coherency memory system

A multiprocessor computer system comprising:

• a plurality of processors;
• a plurality of data cache memories, at least one data cache memory associated with each one of said processors;
• a processor line status table (PLST) associated with each of said data cache memories said PLST comprising Modified-Exclusive-Shared-Invalid (MESI) state bits;
• a system memory shared by said multiple processors;
• a system of busses interconnecting said system memory with said plurality of data cache memories and said multiple processors;
• and
• a state cache memory associated with said shared system memory and connected to said system of busses for the storage of a memory line status table (MLST), said MLST to store memory line state information identifying where within said plurality of data cache memories a copy of a line of system memory potentially resides, said memory line state information comprising not cached, share and owned state bits, wherein the PLST associated with each of the identified data cache memories indicates local state information for the copy of the line of system memory.

A multiprocessor computer system, comprising:

• a plurality of processors;
• a plurality of data cache memories, at least one data cache memory associated with each one of said processors;
• a system memory shared by said multiple processors;
• first and second memory busses connecting said system memory with said plurality of data cache memories and said multiple processors;
• and
• a centralized/distributed directory-based cache coherency system comprising:
• a Processor Line Status Table (PLST) associated with each data cache memory, each PLST containing state information indicating whether a line of memory within the PLST contains a valid copy of a line of memory within said shared system memory, said PLST comprising Modified-Exclusive-Shared-Invalid (MESI) state bits;
• and
• a state cache memory associated with said shared system memory and connected to said system of busses for the storage of a memory line status table (MLST), said MLST to store memory line state information identifying one of which data cache memories, if any, potentially contain the valid copy of said line of shared system memory, and which of the first and second memory busses, if any, are connected to data cache memories which potentially contain the valid copy of said line of shared system memory, said memory line state information comprising not cached, shared, and owned state bits.