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AssigneeInternational Business Machines Corporation
InventorsCharles Roberts Moore, John Stephen Muhich, Brian James Vicknair
Estimating the term…
A method and system are efficiently maintaining data coherency in a multiprocessor data processing system having multiple processors coupled together via common bus. Each time an attempted modification is made to selected data by one of the processors, a multistate bus synchronization flag is established within the initiating processor. A bus operation request which is appropriate for the type of data modification is then issued from a cache associated with the initiating processor to a memory queue associated therewith. The bus operation request is then transmitted onto the common bus from the memory queue on an opportunistic basis, permitting additional cache operations to occur during the pendency of the bus operation request. A successful assertion of the bus operation request, indicating no coherency problems exist with respect to other processors, results in an alteration of the state of the multistate bus synchronization flag, permitting modification of the selected data. A failure to successfully assert the bus operation request will result in the automatic reissue of the bus operation request, greatly enhancing the ability of the system to maintain data coherency.
A method in a multiprocessor system having a plurality of processors coupled together via a common bus for efficient maintenance of data coherency among main storage and multiple cache memories within said multiprocessor system, said method comprising the steps of:
A system for efficient maintenance of data coherency among main storage and multiple cache memories within a multiprocessor system having a plurality of processors coupled together via a common bus, said system comprising:
Dependencies are inferred from the claim text.