Method for providing both level-sensitive and edge-sensitive interrupt signals on a serial interface between a peripheral and host

A method for generating an Interrupt Signal on a serial data interface line for communication from a peripheral device to a host having either a level-sensitive or an edge-sensitive interrupt detector, comprising the steps of:

• A. receiving an active Interrupt Signal request and responsive thereto determining if Chip Select from the host processor is released, and
• B. responsive to Chip Select being released, generating the Interrupt Signal in a serial data interface format by;
• B1. transitioning and maintaining the Interrupt Signal to active level,
• B2. receiving an active Chip Select Signal and multiple Clock pulses from the host processor as confirmation of receipt of the Interrupt Signal, and responsive thereto transitioning the Interrupt Signal from active to inactive level, and
• B3. transitioning and maintaining the Interrupt Signal from inactive to active level responsive only to the Interrupt Signal request still being active and Chip Select being released,
• whereby the active level of the Interrupt Signal on the serial data interface line from the peripheral in step B1 will activate level-sensitive detectors and the combination of transitions in steps B1, B2 and B3 will activate edge-sensitive detectors.

A circuit for generating an Interrupt Signal, compatible with either a level-sensitive or an edge-sensitive interrupt detector, over a serial data interface line for communication from a peripheral device to a host processor generally coupled together with at least lines for Interrupt, Chip Select, and System Clock Signals, comprising:

• a first circuit for receiving an active Interrupt Signal request and responsive thereto determining if a Chip Select Signal from the host processor is released,
• a control circuit, coupled to said first circuit and the serial data interface line, actuated only responsive to the Chip Select Signal being released, for generating said Interrupt Signal in a serial data interface format, said control circuit comprising;
• a second circuit for transitioning and maintaining said Interrupt Signal to active,
• a third circuit for receiving an active Chip Select signal and multiple Clock pulses from the host processor as confirmation of receipt of said Interrupt Signal, and responsive thereto transitioning said Interrupt Signal from active to inactive, and
• a fourth circuit for transitioning and maintaining said Interrupt Signal from inactive to active responsive only to the Interrupt Signal request still being active and Chip Select being released,
• whereby the level of said Interrupt Signal on the serial data interface line from said second circuit will activate level-sensitive detectors and the combination of transitions from said second and fourth circuits will activate edge-sensitive detectors in the host processor.

A circuit for generating an Interrupt Signal, compatible with either level-sensitive or an edge-sensitive interrupt detectors coupled to a serial data interface line, for communication from a peripheral device to a host processor generally coupled together with at least lines for Interrupt, Chip Select, and System Clock Signals, comprising:

• a first circuit for receiving an active Interrupt Signal request and responsive thereto determining if a Chip Select Signal from the host processor is released,
• a control circuit, coupled to said first circuit and the serial data interface line and actuated only responsive to the Chip Select Signal being released, for generating said Interrupt Signal in a serial data interface format, said control circuit comprising;
• a second circuit, comprising one of an AND gate and a NAND gate, for transitioning and maintaining said Interrupt Signal to active,
• a third circuit for receiving an active Chip Select signal and multiple Clock pulses from the host processor as confirmation of receipt of said Interrupt Signal, and responsive thereto transitioning said Interrupt Signal from active to inactive, wherein said third circuit comprises a divide by 8 counter coupled to and for counting said at least 8 clock pulses from the host, and a logical AND gate coupled thereto for transitioning said Interrupt Signal responsive to receiving both the 8 clock pulses and the Chip Select Signal, and
• a fourth circuit for transitioning and maintaining said Interrupt Signal from inactive to active responsive only to the Interrupt Signal request still being active and Chip Select being released,
• whereby the level of said Interrupt Signal on the serial data interface line from said second circuit will activate level-sensitive detectors and the combination of transitions from said second, third and fourth circuits will activate edge-sensitive detectors.