Branch predicting mechanism for enhancing accuracy in branch prediction by reference to data
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorTetsuya Hara
Life of this patent
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Abstract
A branch predicting apparatus includes a prediction information buffer for supplying prediction information related to branch prediction of a branch instruction, at a same timing as fetching of an instruction fetched before the branch instruction, and a branch predicting mechanism for reading, if necessary, information required for branch prediction from a register file storing a result of operation of an instruction pipeline in accordance with the prediction information supplied from the prediction information buffer, performing branch prediction of the branch instruction by, at the latest, completion of the fetch cycle of the branch instruction, and for outputting a branch prediction signal.
Claims22
A branch predicting apparatus in a processor of a pipelined architecture, having means for storing a result of operation, comprising:
- prediction information supplying means for supplying at a same timing as fetching of an instruction fetched before a branch instruction, prediction information related to branch prediction of a branch instruction, the prediction information specifying where information to be referred to by the branch instruction is stored in said means for storing;
- and
- branch predicting means for reading, if necessary, information, specified by said prediction information necessary for branch prediction, from said means for storing, for performing branch prediction of said branch instruction by, at the latest, completion of a fetch cycle of said branch instruction and for outputting a branch prediction signal used in prefetching instructions to be executed subsequent to said branch instruction.
A branch predicting apparatus in a processor of a pipelined architecture, comprising:
- program relative instruction immediate value storing means for storing, when a branch instruction of a program counter relative is executed, an immediate value of an offset of the program counter by said branch instruction in association with an address of a instruction having a prescribed relation with said branch instruction;
- means for reading, simultaneously with next fetching of said instruction, an immediate value if any, which is stored in said program relative instruction immediate value storing means associated with the address of said instruction;
- and
- branch predicting means responsive to the immediate value being read from said program relative instruction immediate value storing means, for predicting direction of branching of the branch instruction associated with the fetched instruction in accordance with a prescribed scheme, and for performing branch target prediction by using said read immediate value.
A branch predicting apparatus in a processor of a pipelined architecture, comprising:
- branch prediction information storing means for storing branch prediction information associated with an address of an instruction having a prescribed relation with a branch instruction when said branch instruction is executed, said branch prediction information including calculation method specifying information for specifying a method of calculating branch target of said branch instruction, and branch target calculation information used for calculating branch target in executing the branch instruction;
- means for reading branch prediction information, if any, which is stored in said branch prediction information storing means associated with the address of the instruction, simultaneously with fetching of said instruction;
- and
- branch predicting means responsive to branch prediction information being read from said branch prediction information storing means for predicting a direction of branching in accordance with a prescribed scheme, and for predicting a branch target of the branch instruction associated with the fetched instruction by performing calculation on the branch target calculation information of said read branch prediction information, in accordance with a method of calculation specified by the calculating method specifying information of said read branch prediction information.
A branch predicting apparatus in a processor of a pipelined architecture, comprising:
- a plurality of registers each storing prediction information related to branch prediction of a branch instruction, said prediction information indirectly indicating data to be referenced in execution of a branch instruction;
- specifying information supplying means for supplying specifying information for specifying one of said plurality of registers that stores branch prediction information of a branch instruction, at a same timing as fetching of an instruction fetched before said branch instruction;
- and
- branch predicting means for reading the branch predicting information of said branch instruction from that one of said plurality of registers which is specified by the specifying information supplied from said specifying information supplying means, performing branch prediction of said branch instruction by, at the latest, completion of a fetch cycle of said branch instruction, and for outputting a branch predicting signal used in prefetching instructions to be executed subsequent to the branch instruction.
Dependencies are inferred from the claim text.