US 5,848,267 A · Computer system speed control using memory refresh counter

Abstract

A computer system which provides for slowing the effective speed of a microprocessor. The microprocessor includes a disabling input that when deactivated disables operations of the microprocessor on the processor bus. A computer system according to the invention periodically deasserts this signal with the certain duty cycle, allowing the microprocessor to continue to perform necessary functions at an effective rate compatible with older microprocessors, but never requiring an actual clock frequency change. This periodic deassertion is performed in response to a memory refresh counter that periodically counts down to zero and is reloaded. By comparing an input/output register with the refresh counter, and by adjusting the input/output register, the deasserting signal to the processor is periodically deasserted with a selectable duty cycle.

Claims17

Dependent claims

A method of reducing effective microprocessor speed in a computer system, the computer system including a refresh counter and a microprocessor having a disabling input, the method comprising the steps of:

detecting with a first comparator that the refresh counter has reached a first predetermined count;
asserting a disabling signal coupled to the disabling input in response to said detecting of said first predetermined count;
detecting with a second comparator that the refresh counter has reached a second predetermined count;
deasserting said disabling signal in response to said detecting of said second predetermined count;
detecting with a third comparator that the refresh counter has reached a third predetermined count;
and
invoking a refresh cycle in response to said detecting of said third predetermined count,
wherein said firs, second, and third comparators are different comparators.

5 more elements

A computer system with microprocessor speed control, comprising:

a bus with address and control lines;
a microprocessor coupled to said bus, said microprocessor having a disabling input;
a peripheral storage device coupled to said bus;
a memory subsystem coupled to said bus;
a memory controller for controlling said memory subsystem;
a refresh counter that periodically provides a refresh signal to said memory controller, causing said memory controller to initiate a refresh of said memory subsystem;
and
a speed control circuit, comprising:
a first compare circuit coupled to said refresh counter, said first compare circuit providing an indication of when said refresh counter reaches a first predetermined count;
a second compare circuit coupled to said refresh counter, said second compare circuit providing an indication of when said refresh counter reaches a second predetermined count;
microprocessor disable and enable logic, said logic coupled to said first compare circuit, said second compare circuit and the disabling input of said microprocessor, said microprocessor disable and enable logic providing a disabling signal to the disabling input in response to the indication that the refresh counter has reached the first predetermined count, and providing an enabling signal to the disabling input in response to the indication that the refresh counter has reached the second predetermined count;
and
a third compare circuit coupled to said refresh counter, said third compare circuit providing a refresh signal,
wherein said three compare circuits are different circuits, and
wherein said refresh counter is a single counter.

12 more elements

Dependencies are inferred from the claim text.

Computer system speed control using memory refresh counter

Life of this patent

Computer system speed control using memory refresh counter

Life of this patent

Abstract

Claims17