Memory bank addressing scheme

Abstract

In accordance with the present invention, an apparatus includes a system bus having memory bank identification signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank, and at least one commander module. The commander module contains decode logic which includes memory mapping registers associated with unique values to be driven on the memory bank identification signals. The memory banks contain compare logic including a virtual node identification register which stores a predetermined value to be compared with the value driven on the memory bank identification signals to determine if the memory bank is the target of the current transaction. Thus, memory banks need not decode the entire system bus address to determine if they are the target of the transaction which reduces the time required to complete a transaction with memory. Further, the apparatus allows memory modules having a different number of memory banks and memory banks capable of storing a different number of addressable locations to be efficiently used in the same computer system.

Dependencies are inferred from the claim text.