Method and apparatus for address disambiguation using address component identifiers

A computer system, comprising:

• a bus;
• a memory coupled to the bus;
• a processor, coupled to the bus, having a scheduling unit that schedules an execution order of a first instruction of a first type and a second instruction of a second type in an instruction stream where the second instruction precedes the first instruction, including a address disambiguation table that records address component identifiers corresponding to the second instruction, and an address comparator that compares address component identifiers that correspond to the first instruction with address component identifiers on the address disambiguation table, the scheduling unit scheduling the first instruction to be executed ahead of the second instruction when the address component identifiers that correspond to the first instruction differ from the address component identifiers on the address disambiguation table.

A method for determining when to execute a first instruction of a first type ahead of a second instruction of a second type in an instruction stream where the second instruction precedes the first instruction, comprising:

• recording address component identifiers corresponding to the second instruction on a address disambiguation table;
• comparing address component identifiers that corresponds to the first instruction with address component identifiers on the address disambiguation table;
• executing the first instruction ahead of the second instruction if the address component identifiers corresponding to the first instruction differ from the address component identifiers on the address disambiguation table.

A method for determining when to execute a first instruction of a first type ahead of a second instruction of a second type in an instruction stream where the second instruction precedes the first instruction, comprising:

• comparing address component identifiers corresponding to the first instruction with address component identifiers corresponding to the second instruction;
• executing the first instruction before the second instruction if the address component identifiers corresponding to the first instruction are not the same as the address component identifiers of the second instruction.