Method and apparatus for enabling intelligent I/O subsystems using PCI I/O devices

Abstract

An apparatus having a first interface for coupling to a first component bus; a second interface for coupling to a second component bus; an address translation unit coupled to the second interface; and a bus bridge coupled to the first interface and to the second interface. The bus bridge has a first configuration register for disabling an assertion by a first component coupled to the first interface of a component select signal on said second interface; a second configuration register for disabling a propagation by the bus bridge of a private address, contained in an address space which is private to the second interface, from the second interface to the first interface, and to disable a response by the bus bridge to the private address sent from the first interface; and a third configuration register in the address translation unit such that the address translation unit will translate the private address to a local system address in a local system address space, and also translate a local system address contained in the local system address space to the private address.

Dependencies are inferred from the claim text.