Programmable digital filter for stable interval detection
AssigneeIntel Corporation
InventorsLeonard Cross, David W. Bogardus
Life of this patent
Estimating the term…
Abstract
A programmable digital filter. The digital filter detects a predefined pattern over a programmably variable duration. The filter includes an interval register which is coupled to receive an interval count. A sample register is coupled to receive a plurality of samples of an input signal which is sampled at an interval determined by the interval count. A plurality of pattern matching circuits generate a pattern match output if the plurality of samples matches one of a plurality of predetermined patterns, and a state logic circuit generates a signal if a new match is found. The pattern matching circuits may be stable high and stable low test circuits which cooperate to determine if all of the plurality of samples are of a consistent logic value.
Claims27
A digital filter comprising:
- an interval register coupled to receive an interval count;
- a sample register coupled to receive a plurality of samples of an input signal sampled at a sampling interval determined by said interval count;
- a plurality of pattern matching circuits coupled to generate a pattern match output if said plurality of samples matches one of a plurality of predetermined patterns;
- and
- state logic coupled to generate a change state signal if said pattern match output indicates a new match.
A programmable digital filter comprising:
- a register which is coupled to sample an input signal in response to a sample enable signal, and which contains a plurality of samples of said input signal;
- a stability test circuit which is coupled to receive said plurality of samples in parallel and has a stability test output indicating whether said plurality of samples are all a consistent logic value;
- a programmable filter duration register which contains a duration indicator;
- and
- a filter interval circuit coupled to provide said sample enable signal at a frequency defined by said duration indicator.
In a computer system having a processor and a memory subsystem coupled to a bus comprising a plurality of address and data lines, a peripheral device coupled to said bus, coupled to receive an input signal, and coupled to interrupt said processor, the peripheral device comprising:
- a filter duration register which is coupled to receive a filter duration value from the bus;
- a filter interval circuit which is coupled to said filter duration register and provides a sampling signal at an interval determined using said filter duration register;
- and
- a stability test circuit which is coupled to sample said input signal according to said sampling signal, and which generates a stability test output indicating whether a plurality of samples are all a consistent logic value, said peripheral device interrupting said processor responsive to said stability test output.
A method of providing stable interval detection comprising the steps of:
- (a) sampling one of a plurality of sampled values;
- (b) waiting a predetermined amount of time;
- (c) repeating steps (a) and (b) for said plurality of sampled values;
- (d) determining if said sampled values represent a stable state;
- and
- (e) generating an interrupt signal if said stable state differs from a prior stable state.
Dependencies are inferred from the claim text.