Test device employing scan path having circuitry at switches between a scan in signal transmitted and previously held at a predetermined clock timing

Abstract

A test device which employs a scan path method includes a latch circuit for holding a scan in signal, a transfer gate connected between the scan in signal and an input terminal of the latch circuit and having a gate terminal receiving a clock signal, a select circuit for selecting one of a data signal and an output signal from the latch circuit in response to a mode select signal and for outputting the selected signal, and a flipflop circuit for holding an output signal from the select circuit in response to the clock signal and for outputting the held signal as a scan out signal.

Dependencies are inferred from the claim text.