Method and device for testing content addressable memory circuit and content addressable memory circuit with redundancy function
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHideshi Maeno
Life of this patent
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Abstract
Automatic generation of a test pattern for test data to test a content addressable memory for failure is disclosed. An inverter (INV1) inverts a scan signal (SODI) outputted from a scan path to apply the inverted scan signal to a 1-input of a selector (SEL1). A scan input (SIDI) is the inverted version of a scan output from a scan flip-flop (SFF-D12). To test a content addressable memory (100), a test signal (CAMTEST) is set to "1", thereby producing input signals (DI0, DI1, DI2) in such a looped manner as: (0, 0, 0).fwdarw.(1, 0, 0).fwdarw.(1, 1, 0).fwdarw.(1, 1, 1).fwdarw.(0, 1, 1).fwdarw.(0, 0, 1).fwdarw.(0, 0, 0).fwdarw. . . . .
Claims20
A method of testing a content addressable memory circuit having an m by n array of content addressable memory cells and n match signal lines, each of said content addressable memory cells being located at an intersection of an i-th column, with 0.ltoreq.i.ltoreq.n-1, and a j-th row, with 0.ltoreq.j.ltoreq.m-1, in said array, said method comprising the steps of:
- initializing all of said content addressable memory cells with a set of initial logic value for each column of said array;
- forming an initial pattern including m input signals corresponding to said set of initial logic value;
- inverting the logic value of one of said m input signals of said initial pattern to form a test pattern;
- conducting a search operation with said test pattern in said content addressable memory circuit by applying said test pattern to the content addressable memory cells in said array while checking signals on said n match signal lines;
- and
- writing said test pattern into an i-th column and updating a column number i.
A test circuit for testing a content addressable memory circuit having an m by n array of content addressable memory cells and n match signal lines, each of said content addressable memory cells being located at an intersection of an i-th column, with 0.ltoreq.i.ltoreq.n-1, and a j-th row, with 0.ltoreq.j.ltoreq.m-1, in said array, said test circuit comprising:
- a first inverter having an input and an output;
- m scan flip-flops for input corresponding to each of m rows of said array, said m scan flip-flops for input each having a scan input and a scan output, said m scan flip-flops for input forming a scan path having a serial input and a serial output with said m scan flip-flops for input being connected in series with a said scan input of one of said m scan flip-flops for input being connected to a said scan output of another of said m scan flip-flops for input, and said scan path being controlled by a clock supplying a same clock signal to each of the m scan flip-flops for input;
- wherein said serial input of said scan path is connected to said output of said first inverter;
- wherein said serial output of said scan path is connected to said input of said first inverter;
- wherein a j-th one of said m scan flip-flops for input holds a j-th input signal to be written into each j-th row of said array for each of said n columns of said arrays;
- and
- wherein a content held in the j-th row of said array is searched in said content addressable memory circuit.
A content addressable memory circuit with redundancy function having zeroth to (n-1)-th columns of content addressable memory cells arranged in m rows each, and an n-th column of content addressable memory cells arranged in m rows, said content addressable memory circuit with redundancy function for determining whether or not external test data match comparison data stored in said zeroth to n-th columns of content addressable memory cells, said content addressable memory circuit with redundancy function comprising:
- (a) an output portion for storing an i-th acceptance/failure data indicative of an active/inactive state when an i-th column of content addressable memory cells are acceptable/failed to output an i-th coincidence determination signal candidate and an n-th coincidence determination signal candidate, wherein 0.ltoreq.i.ltoreq.n-1, and said i-th coincidence determination signal candidate indicating whether or not said comparison data stored in said i-th column of content addressable memory cells match said test data, said n-th coincidence determination signal candidate indicating whether or not said comparison data stored in said i-th column of content addressable memory cells match said test data;
- (b) a first control circuit receiving said zeroth to (n-1)-th acceptance/failure data and said zeroth to n-th coincidence determination signal candidates and including,
- (b-1) a group of gates outputting zeroth to (n-1)-th control signals, and
- (b-2) a group of selectors for outputting as an i-th coincidence determination signal said i-th coincidence determination signal candidate or an (i+1)-th coincidence determination signal candidate in response to an active/inactive state of said i-th control signal;
- (c) a second control circuit receiving first to n-th column specifying raw signals corresponding respectively to said zeroth to (n-1)-th columns of content addressable memory cells and alternatively activated, said second to n-th control signals, and said first to n-th acceptance/failure data and including,
- (c-1) a group of selectors for outputting as a (t+1)-th column specifying signal candidate, with 0.ltoreq.t.ltoreq.n-2, and a t-th column specifying raw signal or said (t+1)-th column specifying raw signal in response to an active/inactive state of a t-th control signal, and outputting as an n-th column signal specifying candidate said (n-1)-th column specifying raw signal or "0" in response to an inactive/active state of said (n-1)-th control signal, and
- (c-2) a group of gates for determining an AND state of said i-th column specifying signal candidate and said i-th acceptance/failure data to output an i-th column specifying signal;
- said group of gates of said first control circuit outputting said zeroth acceptance/failure data as said zeroth control signal and an AND state of a k-th acceptance/failure data and a (k-1)-th control signal as a k-th control signal, with 1.ltoreq.k.ltoreq.n-1;
- said zeroth column specifying signal candidate being said zeroth column specifying raw signal;
- said n-th column specifying signal candidate being said n-th column specifying signal;
- and
- said zeroth to n-th columns of content addressable memory cells being selected in response to said zeroth to n-th column specifying signals.
A content addressable memory circuit with redundancy function having zeroth to (m-1)-th rows of content addressable memory cells arranged in n columns each, and an m-th row of content addressable memory cells arranged in n columns, said content addressable memory circuit with redundancy function for determining whether or not external test data match comparison data stored in said zeroth to n-th columns of content addressable memory cells, said content addressable memory circuit with redundancy function comprising:
- (a) an output portion receiving the outputs from said zeroth to m-th rows of content addressable memory cells and their associated expected values to output zeroth to m-th acceptance/failure data and zeroth to m-th output signal candidates, said zeroth to m-th acceptance/failure data being active/inactive when said zeroth to m-th rows of content addressable memory cells are acceptable/failed, respectively, said zeroth to m-th output signal candidates being the outputs from said zeroth to m-th rows of content addressable memory cells;
- (b) a j-th input scan flip-flop, with 0.ltoreq.j.ltoreq.m, including a selector, said j-th input scan can flip-flop having,
- (b-1) a scan input terminal,
- (b-2) a flip-flop, and
- (b-3) a scan output terminal having a first input connected to said scan input terminal, a second input connected to said scan input terminal through said flip-flop, and an output connected to said first or second input when said j-th acceptance/failure data is active/inactive, respectively;
- wherein zeroth to m-th input scan flip-flops are sequentially connected in series;
- and
- (c) an inverter having an input connected to an m-th scan output terminal of an m-th scan flip-flop, and an output connected to a zeroth scan input terminal of a zeroth scan flip-flop.
Dependencies are inferred from the claim text.