Clock controlled column decoder

Abstract

A column decoder of a semiconductor memory device operates in synchronism to an external system clock to decode externally-supplied column addresses. The column decoder has a column select line enable unit which decodes the externally-supplied column addresses and generates a plurality of predecoded column addresses. The column decoder uses a predecoder to predecode the externally-supplied column addresses and generate the predecoded column addresses. The column select line enable unit also uses the predecoder to sample one of the predecoded column addresses in synchronism to the external system clock using an automatic control clock, thereby enabling a column select line. A precharge pulse generator latches one of the predecoded column addresses in response to a first level of the external system clock, triggers to the latched signal in response to a second level of the external system clock, and thereby generates a precharge pulse which is delayed by a specified amount. A column select line enable circuit enables the column select line in response to an enable clock by combining the sampled predecoded column address with the other predecoded column addresses, and which disables the column select line in response to the precharge pulse. The column decoder of the present invention allows for the control of a generation time of the precharge pulse and for the adjusting of a disable interval of the column select line to enhance operation of the column decoder over a wide range of operating frequencies of the semiconductor memory device.

Dependencies are inferred from the claim text.