Back to results
US 5,848,023 AGranted
Semiconductor memory device operable in burst mode and method of controlling the same
AssigneeNEC Corporation
InventorsYoshiyuki Kato, Junji Monden
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeNEC Corporation
InventorsYoshiyuki Kato, Junji Monden
Estimating the term…
A circuit for generating memory cell array block selective signals which select memory cell array blocks included in a semiconductor memory device operable in burst mode, wherein the circuit is operated under the control of a burst mode control signal to generate memory cell array block selective signals sequentially and one by one through different and successive time cycles so that, according to the memory cell array block selective signals sequentially generated, the memory cell array blocks are also sequentially selected one by one through the different and successive time cycles for sequentially supplying a word line driver circuit with the memory cell array block selective signals one by one through the different and successive time cycles whereby memory cells included in different memory cell array blocks are sequentially selected one by one through the different and successive time cycles.
A semiconductor memory device operable in burst mode and having a predetermined block number of memory cell array blocks, in each of which a predetermined cell number of memory cells are aligned, said semiconductor memory device comprising:
A semiconductor memory device operable in burst mode and having a predetermined block number of memory cell array blocks, in each of which a predetermined cell number of memory cells are aligned, said semiconductor memory device comprising:
A circuitry for generating memory cell array block selective signals which select memory cell array blocks included in a semiconductor memory device operable in burst mode, said circuitry being operated under the control of a burst mode control signal to generate memory cell array block selective signals sequentially and one by one through different and successive time cycles so that, according to said memory cell array block selective signals sequentially generated, said memory cell array blocks are also sequentially selected one by one through said different and successive time cycles for sequentially supplying a word line driver circuit with said memory cell array block selective signals one by one through said different and successive time cycles whereby memory cells included in different memory cell array blocks are sequentially selected one by one through said different and successive time cycles.
A method of controlling reading out/writing up operations of continuous address data in burst mode to memory cells aligned in memory cell array blocks, wherein under the control of a burst mode control signal, memory cell array block selective signals are sequentially generated one by one through different and successive time cycles so that, according to said memory cell array block selective signals sequentially generated, said memory cell array blocks are also sequentially selected one by one through said different and successive time cycles for sequentially supplying a word line driver circuit with said memory cell array block selective signals one by one through said different and successive time cycles whereby memory cells included in different memory cell array blocks are sequentially selected one by one through said different and successive time cycles.
Dependencies are inferred from the claim text.