US 5,848,022 AGranted

Address enable circuit in synchronous SRAM

AssigneeIntegrated Silicon Solution, Inc.

InventorYong H. Jiang

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Abstract

A novel address enable circuit for use in a synchronous memory that includes a memory core. The address enable circuit includes an address latching circuit that outputs a synchronized address and latches a pre-decoded address when an input clock signal transitions from a first logical level to a second logical level so that the synchronized address identifies the pre-decoded address. The address enable circuit also includes a reset circuit that generates a reset signal that (1) does not indicate a reset when the latched chip enable signal indicates that the memory has been selected while the clock signal is at the second logical level, (2) indicates a reset when the latched chip enable signal indicates that the memory has not been selected while the clock signal is at the second logical level, and (3) does not indicate a reset while the clock signal is at the first logical level. The address latching circuit is reset when the reset signal indicates a reset so that the synchronized address identifies a disabled address that indicates that memory access to the memory core is disabled and is not reset when the reset signal does not indicate a reset.

Claims12

Dependent claims

An address enable circuit for use in a synchronous memory that includes a memory core, the address enable circuit comprising:

a chip enable decoding circuit that decodes input chip enable signals to generate a decoded chip enable signal that indicates whether the memory has been selected;
a chip enable latching circuit that latches the decoded chip enable signal to generate a latched chip enable signal when an input clock signal transitions from a first logical level to a second logical level;
an address pre-decoding circuit that pre-decodes an input address to generate a pre-decoded address that is distinct from a predefined disabled address that indicates that memory access to the memory core is disabled;
an address latching circuit that latches the pre-decoded address when the input clock signal transitions from the first logical level to the second logical level so as to output a synchronized address that identifies the pre-decoded address;
a reset circuit that generates a reset signal that (1) does not indicate a reset when the latched chip enable signal indicates that the memory has been selected while the clock signal is at the second logical level, (2) indicates a reset when the latched chip enable signal indicates that the memory has not been selected while the clock signal is at the second logical level, and (3) does not indicate a reset while the clock signal is at the first logical level;
the address latching circuit (1) being reset when the reset signal indicates a reset so that the synchronized address identifies the disabled address, and (2) not being reset when the reset signal does not indicate a reset so that the synchronized address continues to identify the pre-decoded address;
a drive circuit that drives the memory core with the synchronized address.

4 more elements

A method of driving a memory core of synchronous memory with a synchronous address, the method comprising the steps of:

decoding input chip enable signals to generate a decoded chip enable signal that indicates whether the memory has been selected;
latching the decoded chip enable signal to generate a latched chip enable signal when an input clock signal transitions from a first logical level to a second logical level;
pre-decoding an input address to generate a pre-decoded address that is distinct from a predefined disabled address that indicates that memory access to the memory core is disabled;
latching the pre-decoded address when the input clock signal transitions from the first logical level to the second logical level so as to output a synchronized address that identifies the pre-decoded address;
generating a reset signal that (1) does not indicate a reset when the latched chip enable signal indicates that the memory has been selected while the clock signal is at the second logical level, (2) indicates a reset when the latched chip enable signal indicates that the memory has not been selected while the clock signal is at the second logical level, and (3) does not indicate a reset while the clock signal is at the first logical level;
resetting the synchronized address to identify the disabled address when the reset signal indicates a reset;
not resetting the synchronized address when the reset signal does not indicate a reset so that the synchronized address continues to identify the pre-decoded address;
and
driving the memory core with the synchronized address.

6 more elements

Dependencies are inferred from the claim text.